2002 |
4 | EE | Ohsang Kwon,
Kevin J. Nowka,
Earl E. Swartzlander Jr.:
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells.
VLSI Signal Processing 31(2): 77-89 (2002) |
2001 |
3 | EE | Ohsang Kwon,
Earl E. Swartzlander Jr.,
Kevin J. Nowka:
A fast hybrid carry-lookahead/carry-select adder design.
ACM Great Lakes Symposium on VLSI 2001: 149-152 |
2000 |
2 | EE | Ohsang Kwon,
Earl E. Swartzlander Jr.,
Kevin J. Nowka:
A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors.
ASAP 2000: 235- |
1 | EE | Stephen D. Posluszny,
N. Aoki,
David Boerstler,
P. Coulman,
Sang H. Dhong,
Brian K. Flachs,
H. Peter Hofstee,
N. Kojima,
Ohsang Kwon,
K. Lee,
D. Meltzer,
Kevin J. Nowka,
J. Park,
J. Peter,
Joel Silberman,
Osamu Takahashi,
Paul Villarrubia:
"Timing closure by design, " a high frequency microprocessor design methodology.
DAC 2000: 712-717 |