The Journal of VLSI Signal Processing, Volume 2

Volume 2, Number 1, September 1990

• Earl E. Swartzlander Jr.:
  Editorial. 5
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• Tom Kean, John Gray:
  Configurable hardware: Two case studies of micro-grain computation. 9-16
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• Luigi Dadda:
  A polyphase architecture for serial-input convolvers. 17-27
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• Paul S. Lewis:
  Systolic architectures for adaptive multichannel least squares lattice filters. 29-36
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• F. M. F. Gaston, George W. Irwin, J. G. McWhirter:
  Systolic square root covariance Kalman filtering. 37-49
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• Stuart Lawson, Steve Summerfield:
  The design of wave digital filters using fully pipelined bit-level systolic arrays. 7
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Volume 2, Number 2, October 1990

• John A. Graniero, Claud N. Bain:
  Introduction. 67
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• Daniel J. Dechant:
  The Advanced Onboard Signal Processor (AOSP). 69-78
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• M. J. Little, R. David Etchells, Jan Grinberg, S. P. Laub, J. G. Nash, M. W. Yung:
  The 3-D Computer. 79-87
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• M. J. Iacoponi:
  The Advanced Architecture On-board Processor signal processing testbed. 89-101
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• G. Melcher, G. Thomas, D. Kaplan:
  The Navy's new standard digital signal processor, the AN/UYS-2. 103-109
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• Earl E. Swartzlander Jr.:
  Generic signal processor implementation with VHSIC. 111-116
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• J. B. Clary:
  Signal processing architecture assessment. 117-121
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Volume 2, Number 3, November 1990

• Graham A. Jullien, Subir Bandyopadhyay, William C. Miller, M. Taheri:
  A low-overhead scheme for testing a bit-level finite ring systolic array. 131-137
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• Mark R. Greenstreet, Kenneth Steiglitz:
  Bubbles can make self-timed pipelines fast. 139-148
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• M. Yan, John V. McCanny:
  A bit-level systolic architecture for implementing a VQ tree search. 149-158
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• Thomas L. Wernimont, David K. Hwang, W. Kent Fuchs:
  CSP-based object-oriented description and simulation of a reconfigurable adaptive beamforming architecture using the OODRA workbench. 159-172
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• Sy-Yen Kuo, Kuochen Wang:
  Fault diagnosis in reconfigurable VLSI and WSI processor arrays. 173-187
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Volume 2, Number 4, May 1991

• Virginio Cantoni, V. Gesu, Marco Ferretti, Stefano Levialdi, Roberto M. Negrini, Renato Stefanelli:
  The PAPIA system. 195-217
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• Richard C. North, Walter H. Ku:
  beta-bit serial/parallel multipliers. 219-233
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• Wayne P. Burleson, Louis L. Scharf:
  A VLSI design methodology for distributed arithmetic. 235-252
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• Vijay K. Jain, David L. Landis, David C. Keezer, K. T. Wilson, D. Whittaker:
  Wafer Scale Integration: A university perspective. 253-269
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• R. M. Lea:
  WASP: A WSI Associative String Processor. 271-285
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• Marios D. Dikaiakos, Kenneth Steiglitz:
  Comparison of tree and straight-line clocking for long systolic arrays. 287-299
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• Ron Bourassa, Tim Coffman, Joe Brewer:
  Ultra large scale static rams. 301-311
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• Poras T. Balsara, Mary Jane Irwin:
  Image processing on a memory array architecture. 313-324
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