5. IWSOC 2005:
Banff,
Alberta,
Canada
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada.
IEEE Computer Society 2005, ISBN 0-7695-2403-6 BibTeX
Introduction
Plenary
Semiconductor Technologies
Software/Hardware System Co-design
Manufacturing & Reliability
- Artur Balasinski:
DfM for SoC, invited.
41-46
Electronic Edition (link) BibTeX
- Yoon Huh, Peter Bendix, Kyungjin Min, Jau-Wen Chen, Ravindra Narayan, Larry D. Johnson, Steven H. Voldman:
ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invited.
47-53
Electronic Edition (link) BibTeX
- Azzouz Nezar, Michael Creighton:
System on Chip: Challenges and Design for Manufacturing, invited.
54-59
Electronic Edition (link) BibTeX
- Mohab Anis, Mohamed H. Abu-Rahma:
Leakage Current Variability in Nanometer Technologies, invited.
60-63
Electronic Edition (link) BibTeX
- Nur Kurt-Karsilayan:
Generic Modeling of Non-planar Dielectrics for 2 1/2D Parasitic Extraction.
64-69
Electronic Edition (link) BibTeX
Memories for SoC
- Luca Larcher, Paolo Pavan, A. Maurelli:
Flash Memories for SoC: An Overview on System Constraints and Technology Issues, invited.
73-77
Electronic Edition (link) BibTeX
- Dong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang:
Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits.
78-81
Electronic Edition (link) BibTeX
Analog and Mixed-Signal IC Design
- Farhad Zarkeshvari, Peter Noel, Tad A. Kwasniewski:
PLL-Based Fractional-N Frequency Synthesizers.
85-91
Electronic Edition (link) BibTeX
- M. M. Tabriz, Nasser Masoumi:
A New Topology for Power Control of High Efficiency Class-E Switched Mode Power Amplifier.
92-95
Electronic Edition (link) BibTeX
- Joshua K. Nakaska, James W. Haslett:
A CMOS Quality Factor Enhanced Parallel Resonant LC-Tank with Independent Q and Frequency Tuning for RF Integrated Filters.
96-100
Electronic Edition (link) BibTeX
- Hyoungsoo Kim, Youngsik Hur, Moonkyun Maeng, Franklin Bien, Soumya Chandramouli, Edward Gebara, Joy Laskar:
A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 Signaling.
101-106
Electronic Edition (link) BibTeX
- Shih-Chang Hsia, Wen-Ching Lee:
A Very Low-Power Flash A/D Converter Based on Cmos Inverter Circuit.
107-110
Electronic Edition (link) BibTeX
- Chia-Jung Chang, Ke-Horng Chen:
Bidirectional Current-Mode Capacitor Multiplier in DC-DC Converter Compensation.
111-116
Electronic Edition (link) BibTeX
- Chun-Yueh Huang, Tsung-Tien Hou, Chi-Chieh Chuang, Hung-Yu Wang:
Design of 12-bit 100-MHz Current-Steering DAC for SoC Applications.
117-122
Electronic Edition (link) BibTeX
- Syed Masood Ali, Rabin Raut, Mohamad Sawan:
A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture.
123-126
Electronic Edition (link) BibTeX
- B. Khadem Hosseinieh, N. Masoumi:
A Comprehensive Model for On-Chip Spiral Inductors.
127-131
Electronic Edition (link) BibTeX
- Kenneth A. Townsend, James W. Haslett, Krzysztof Iniewski:
Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits.
132-136
Electronic Edition (link) BibTeX
Digital System Design for SoC
Sensors
- Mohammad Hadi Izadi, Karim S. Karim:
Noise Analysis of a CMOS Active Pixel Sensor for Tomographic Mammography.
167-171
Electronic Edition (link) BibTeX
- Amine Bermak:
Conversion Time Analysis of Time Domain Digital Pixel Sensor in Uniform and Non-Uniform Quantizers, invited.
172-175
Electronic Edition (link) BibTeX
- Yanjie Wang, Yanbin Wang, Garry Tarr, Kris Iniewski:
A Temperature, Supply Voltage Compensated Floating-Gate MOS Dosimeter Using V_TH Extractor.
176-179
Electronic Edition (link) BibTeX
- Haigang Yang, Hongguang Sun, Jinghong Han, Jinbao Wei, Zengjin Lin, Shanhong Xia, Hua Zhong:
A pH-ISFET Based Micro Sensor System on Chip Using Standard CMOS Technology.
180-183
Electronic Edition (link) BibTeX
- Mohammad M. Ahmadi, Graham A. Jullien:
A Very Low Power CMOS Potentiostat for Bioimplantable Applications.
184-189
Electronic Edition (link) BibTeX
Multimedia IP Cores
Wireless Systems
- Robert B. Staszewski, Khurram Muhammad, Dirk Leipold:
Digital RF Processing Techniques for SoC Radios, invited.
217-222
Electronic Edition (link) BibTeX
- Christian Cojocaru:
Low Power Bluetooth for Headset Applications, invited.
223-226
Electronic Edition (link) BibTeX
- N. Patrick Kelly, Ben W. Jones, Nestor A. Fesas, John M. Morton:
Design of 802.11 Access Point Chipsets for Enterprise Applications, invited.
227-232
Electronic Edition (link) BibTeX
- Robert B. Staszewski, Roman Staszewski, Poras T. Balsara:
VHDL Simulation and Modeling of an All-Digital RF Transmitter.
233-238
Electronic Edition (link) BibTeX
- Il-Gu Lee, Heejung Yu, Sok-Kyu Lee, Jin Lee, Sin-Chong Park:
Efficient Pattern-Based Emulation for IEEE 802.11a Baseband.
239-242
Electronic Edition (link) BibTeX
- Yanjie Wang, Kris Iniewski:
A 2.3GHz CMOS Transimpedance Preamplifier for Optical Communication.
243-246
Electronic Edition (link) BibTeX
- Yanjie Wang, M. Zamin Khan, Kris Iniewski:
A 0.65V, 1.9mW CMOS Low-Noise Amplifier at 5GHz.
247-251
Electronic Edition (link) BibTeX
- Daniel Wiklund, Dake Liu:
Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip.
252-256
Electronic Edition (link) BibTeX
- Jung Ko, Vincent C. Gaudet, Robert Hang:
A Tier 3 Software Defined AM Radio.
257-261
Electronic Edition (link) BibTeX
VLSI Physical Design
Towards SoC Design Automation Tools for SoC
- Nasser Masoumi, Mahmoud Ahmadian, Farshid Raissi, Massoud Masoumi, J. Ghasemi:
Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm.
283-288
Electronic Edition (link) BibTeX
- Robert Grou-Szabo, Hany Ghattas, Yvon Savaria, Gabriela Nicolescu:
Component-Based Methodology for Hardware Design of a Dataflow Processing Network.
289-294
Electronic Edition (link) BibTeX
- Li-Chun Tien, Jing-Jou Tang, Mi-Chang Chang:
An Automatic Layout Generator for I/O Cells.
295-300
Electronic Edition (link) BibTeX
- Tina Lindkvist:
Additional Knowledge of Bus Invert Coding Schemes.
301-303
Electronic Edition (link) BibTeX
- Marco Mattavelli, Massimo Ravasi:
High Level Extraction of SoC Architectural Information from Generic C Algorithmic Descriptions.
304-307
Electronic Edition (link) BibTeX
- Abhijit Ray, Thambipillai Srikanthan, Wu Jigang:
Practical Techniques for Performance Estimation of Processors.
308-311
Electronic Edition (link) BibTeX
- Blair Schiffner, Jianhua Li, Laleh Behjat:
A Multivalue Eigenvalue Based Circuit Partitioning Technique.
312-316
Electronic Edition (link) BibTeX
- Haidar Harmanani, Bassem Karablieh:
A Hybrid Distributed Test Generation Method Using Deterministic and Genetic Algorithms.
317-322
Electronic Edition (link) BibTeX
- Russell Klein, Tomasz Piekarz:
Accelerating Functional Simulation for Processor Based Designs, invited.
323-328
Electronic Edition (link) BibTeX
- Ho-Seok Choi, Seungbeom Lee, Sin-Chong Park:
Instruction Based Testbench Architecture, invited.
329-333
Electronic Edition (link) BibTeX
Low-Power SoC
- J. Derakhshandeh, Nasser Masoumi, B. Kasiri, Y. Farazmand, Akbarzadeh, S. Aghnoot:
A Precise Model for Leakage Power Estimation in VLSI Circuits.
337-340
Electronic Edition (link) BibTeX
- Moeed Israr, Tad A. Kwasniewski:
Turbo Codes - Digital IC Design.
341-346
Electronic Edition (link) BibTeX
- Eric Tell, Anders Nilsson, Dake Liu:
A Low Area and Low Power Programmable Baseband Processor Architecture.
347-351
Electronic Edition (link) BibTeX
- Hung-Ch Lee, Kuo-Tai Chang, Ke-Horng Chen, Wen Tsao Chen:
Power Saving of a Dynamic Width Controller for a Monolithic Current-Mode CMOS DC-DC Converter.
352-357
Electronic Edition (link) BibTeX
- Ki-Bog Kim, Chi-Ho Lin:
An Optimal ILP Model for Delay Time to Minimize Peak Power and Area.
358-362
Electronic Edition (link) BibTeX
- Meeta Srivastav, S. S. S. P. Rao, Himanshu Bhatnagar:
Power Reduction Technique Using Multi-vt Libraries.
363-367
Electronic Edition (link) BibTeX
- Payam Ghafari, Ehsan Mirhadi, Mohab Anis, Shawki Areibi, Mohamed I. Elmasry:
A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut Nets.
368-371
Electronic Edition (link) BibTeX
- Dong-Shong Liang, Kwang-Jow Gan, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, Long-Xian Su:
Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits.
372-375
Electronic Edition (link) BibTeX
- Richard Hobson, Scott Wakelin:
An Area-Efficient High-Speed AES S-Box Method.
376-379
Electronic Edition (link) BibTeX
- Sang-Ho Seo, Sin-Chong Park:
Low Latency and Power Efficient VD Using Register Exchanged State-Mapping Algorithm.
380-384
Electronic Edition (link) BibTeX
Digital IP Cores
- Amir Khatibzadeh, Kaamran Raahemifar:
A Novel Design of a 6-GHz 8 X 8-b Pipelined Multiplier.
387-391
Electronic Edition (link) BibTeX
- Kwang-Jow Gan, Dong-Shong Liang, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, Chi-Pin Chen:
Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process.
392-395
Electronic Edition (link) BibTeX
- Shaoqiang Bi, Warren J. Gross, Wei Wang, Asim J. Al-Khalili, M. N. S. Swamy:
An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction.
396-399
Electronic Edition (link) BibTeX
- Kyle Kelley, David Harris:
Very High Radix Scalable Montgomery Multipliers.
400-404
Electronic Edition (link) BibTeX
- Chul-hyung Ryu, Sung-woong Ra:
A Fast Full Search Equivalent Encoding Algorithm for Image Vector Quantization Based on the WHT and a LUT.
405-409
Electronic Edition (link) BibTeX
Programmable and Reconfigurable Cores
- Paul E. Hasler:
Low-Power Programmable Signal Processing, invited.
413-418
Electronic Edition (link) BibTeX
- Mona Safar, M. Watheq El-Kharashi, Ashraf Salem:
An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking.
419-424
Electronic Edition (link) BibTeX
- David N. Abramson, Jordan D. Gray, Shyam Subramanian, Paul E. Hasler:
A Field-Programmable Analog Array Using Translinear Elements.
425-428
Electronic Edition (link) BibTeX
- P. Samson, P. Sinha:
Hardware Acceleration of Deadlock Avoidance and Detection in Real-Time Operating Systems.
429-433
Electronic Edition (link) BibTeX
- Joachim Becker, Fabian Henrici, Yiannos Manoli:
System-Level Analog Simulation of a Mixed-Signal Continuous-Time Field Programmable Analog Array.
434-438
Electronic Edition (link) BibTeX
- Miro Milanovic, Mitja Truntic, Primoz Slibar:
FPGA Implementation of Digital Controller for DC-DC Buck Converter.
439-443
Electronic Edition (link) BibTeX
- A. N. M. Ehtesham Rafiq, M. Watheq El-Kharashi, Fayez Gebali:
Systolic Array-Based String Matching Unit for Spam Blocking.
444-449
Electronic Edition (link) BibTeX
- Esam Khan, M. Watheq El-Kharashi, Fayez Gebali, Mostafa Abd-El-Barr:
An FPGA Design of a Unified Hash Engine for IPSec Authentication.
450-453
Electronic Edition (link) BibTeX
- Bill Pontikakis, François R. Boyer, Yvon Savaria:
Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period.
454-458
Electronic Edition (link) BibTeX
- Paul E. Hasler, AiChen Low:
Programmable Low Dropout Voltage Regulator.
459-462
Electronic Edition (link) BibTeX
Emerging Issue
IP-Blocks for Broadband Networking
- Stephen Bates, Kris Iniewski:
10 GBPS over Copper Lines - State of the Art in VLSI, invited.
491-494
Electronic Edition (link) BibTeX
- Thomas Palkert:
A Review of Current Standards Activities for High Speed Physical Layers, invited.
495-499
Electronic Edition (link) BibTeX
- Miao Li, Peter Noel, Tad A. Kwasniewski, Shoujun Wang:
Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data Communications.
500-502
Electronic Edition (link) BibTeX
- S. M. Rezaul Hasan:
A High Efficiency 3GHz 24-dBm CMOS Linear Power Amplifier for RF Application.
503-507
Electronic Edition (link) BibTeX
- Ching-Te Chiu, Chun-Chieh Chang, Shih-Min Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, Kai-Ming Feng:
A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications.
508-513
Electronic Edition (link) BibTeX
- Vladimir Stojanovic:
High-Speed Serial Links: Design Trends and Challenges, invited.
514
Electronic Edition (link) BibTeX
MPSOC
- Roger Su, Raman Mittal, Vivek Garg:
Synchronous Pipelined Relay Stations with Back-Pressure Tolerance.
517-520
Electronic Edition (link) BibTeX
- Xiqun Zhu, Yuan Ma:
Modular Architecture for System-on-Chip Design of Scalable MEMS Optical Switch Actuator Controller.
521-524
Electronic Edition (link) BibTeX
- Gyongsu Lee, Sin-Chong Park:
Architecture for Multi-processor SoC Platform Using Dedicated Channels.
525-529
Electronic Edition (link) BibTeX
- Sangik Choi, Shinwook Kang:
Implementation of an On-Chip Bus Bridge between Heterogeneous Buses with Different Clock Frequencies.
530-534
Electronic Edition (link) BibTeX
- Zhonghai Lu, Axel Jantsch:
Traffic Configuration for Evaluating Networks on Chips.
535-540
Electronic Edition (link) BibTeX
- Jin Lee, Sin-Chong Park:
Orthogonalized Communication Architecture for MP-SoC with Global Bus.
541-545
Electronic Edition (link) BibTeX
- Luiza Gheorghe, Gabriela Nicolescu:
MP SoCs Including Optical Interconnect. Technological Progresses and Challenges for CAD Tools Design.
546-551
Electronic Edition (link) BibTeX
- Seungbeom Lee, Sin-Chong Park:
Transaction Analysis of Multiprocessor Based Platform with Bus Matrix.
552-556
Electronic Edition (link) BibTeX
- Hung Tien Bui, Yvon Savaria:
A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs.
557-562
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:27:28 2009
by Michael Ley (ley@uni-trier.de)
