Ben C. Drerup
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1994
1
EE
Ben C. Drerup,
Earl E. Swartzlander Jr.
: Fast multiplier bit-product matrix reduction using bit-ordering and parity generation.
VLSI Signal Processing 7
(3): 249-257 (1994)
Coauthor
Index
1
Earl E. Swartzlander Jr.
[
1
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Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
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