Journal of Low Power Electronics, Volume 3

Volume 3, Number 1, April 2007

• Wei-Shen Wang, Michael Orshansky:
  Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters. 1-12
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• Yongkui Han, Israel Koren, C. Mani Krishna:
  TILTS: A Fast Architectural-Level Transient Thermal Simulation Method. 13-21
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• Yang Xu, Hu He, Zhou Zhixiong, Yanjun Zhang, Yihe Sun:
  Heuristic on a Novel Power Management System Cooperating with Compiler. 22-27
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• Anand Ramalingam, Anirudh Devgan, David Z. Pan:
  Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. 28-35
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• Giuseppe Notarangelo, Francesco Pappalardo, Elena Salurso, Elio Guidetti:
  A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing. 36-42
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• Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai:
  Exploiting Speculation Cost Prediction in Power-Aware Applications. 43-53
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• Joachim Fenkes, Tobias Gemmeke, Jens Leenstra:
  Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process. 54-59
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• Steven D. Tucker, Arun Ravindran, Christopher Wichman, Arindam Mukherjee:
  Design Techniques for Micro-Power Algorithmic Analog-to-Digital Converters. 60-69
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• David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo:
  Improving the Performance of Static CMOS Gates by Using Independent Bodies. 70-77
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• Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee:
  Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption. 78-95
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• Domenico Zito, Domenico Pepe, Bruno Neri:
  RFID Systems: Passive versus Active and a Novel Low-Power RF Transceiver for IEEE 802.15.4 (ZigBee) Standard Based Applications. 96-105
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• Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy:
  Low-Power Hierarchical Scan Test for Multiple Clock Domains. 106-118
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