Volume 29,
Number 1,
February 2005
- M. Thaduri, S.-M. Yoo, R. Gaede:
An efficient VLSI implementation of IDEA encryption algorithm using VHDL.
1-7
Electronic Edition (link) BibTeX
- Y. C. Jiang, Z. Y. Xia, Y. P. Zhong, S. Y. Zhang:
An adaptive adjusting mechanism for agent distributed blackboard architecture.
9-20
Electronic Edition (link) BibTeX
- S. B. Wang, S. B. Zhou, G. Huang, B. F. Xiong, S. H. Chen, X. J. Yi:
Fabrication of 128×128 element optical switch array by micromachining technology.
21-25
Electronic Edition (link) BibTeX
- Bruce R. Childers, Jack W. Davidson:
An infrastructure for designing custom embedded wide counterflow pipelines.
27-40
Electronic Edition (link) BibTeX
- Kil-Whan Lee, Woo-Chan Park, Il-San Kim, Tack-Don Han:
A pixel cache architecture with selective placement scheme based on z-test result.
41-46
Electronic Edition (link) BibTeX
Volume 29,
Numbers 2-3,
April 2005
Special Issue on FPGA Tools and Techniques
- Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido:
Advances in FPGA tools and techniques.
47-49
Electronic Edition (link) BibTeX
- Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoungro So, Heidi E. Ziegler:
Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system.
51-62
Electronic Edition (link) BibTeX
- Rolf Enzler, Christian Plessl, Marco Platzner:
System-level performance evaluation of reconfigurable processors.
63-73
Electronic Edition (link) BibTeX
- M. A. Aguirre, Jonathan Noel Tombs, Vicente Baena Lecuyer, J. L. Mora, J. M. Carrasco, Antonio B. Torralba, Leopoldo García Franquelo:
Microprocessor and FPGA interfaces for in-system co-debugging in field programmable hybrid systems.
75-85
Electronic Edition (link) BibTeX
- John A. Nestor:
L3: An FPGA-based multilayer maze routing accelerator.
87-97
Electronic Edition (link) BibTeX
- L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti:
Pseudo-online testing methodologies for various components of field programmable gate arrays.
99-119
Electronic Edition (link) BibTeX
- Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Peter F. Curran, Kuan Zhou, Bryan S. Goda, John F. McDonald:
A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block.
121-131
Electronic Edition (link) BibTeX
Volume 29,
Number 4,
May 2005
Volume 29,
Number 5,
June 2005
Volume 29,
Number 6,
August 2005
- Vasilios Kalenteridis, Haroula Pournara, K. Siozios, Konstantinos Tatas, Nikolaos Vassiliadis, Ilias Pappas, George Koutroumpezis, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris:
A complete platform and toolset for system implementation on fine-grain reconfigurable hardware.
247-259
Electronic Edition (link) BibTeX
- Chunlin Li, Layuan Li:
A distributed decomposition policy for computational grid resource allocation optimization based on utility functions.
261-272
Electronic Edition (link) BibTeX
- Kai-Feng Wang, Zhenzhou Ji, Mingzeng Hu:
Path-based next N trace prefetch in trace processors.
273-288
Electronic Edition (link) BibTeX
- Y. C. Jiang, Z. Y. Xia, S. Y. Zhang:
A novel defense model for dynamic topology network based on mobile agent.
289-297
Electronic Edition (link) BibTeX
- Pasquale Corsonello, Stefania Perri, Paolo Zicari, Giuseppe Cocorullo:
Microprocessor-based FPGA implementation of SPIHT image compression subsystems.
299-305
Electronic Edition (link) BibTeX
Volume 29,
Number 7,
September 2005
Volume 29,
Numbers 8-9,
November 2005
Special Issue on FPGAs:
Case Studies in Computer Vision and Image Processing
- Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido:
Recent advances in computer vision and image processing using reconfigurable hardware.
359-362
Electronic Edition (link) BibTeX
- Manjunath Gangadhar, Dinesh Bhatia:
FPGA based EBCOT architecture for JPEG 2000.
363-373
Electronic Edition (link) BibTeX
- Jesús Lázaro, Jagoba Arias, José Luis Martín, Carlos Cuadrado, Armando Astarloa:
Implementation of a modified Fuzzy C-Means clustering algorithm for real-time applications.
375-380
Electronic Edition (link) BibTeX
- Stefania Perri, Marco Lanuzza, Pasquale Corsonello, Giuseppe Cocorullo:
A high-performance fully reconfigurable FPGA-based 2D convolution processor.
381-391
Electronic Edition (link) BibTeX
- Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses:
The rapid prototyping experience of an H.263 video coder onto FPGA.
393-404
Electronic Edition (link) BibTeX
- N. Sudha:
A pipelined array architecture for Euclidean distance transformation and its FPGA implementation.
405-410
Electronic Edition (link) BibTeX
- Ana Toledo Moreo, Pedro Javier Navarro Lorente, F. Soto Valles, Juan Suardíaz Muro, Carlos Fernández Andrés:
Experiences on developing computer vision hardware algorithms using Xilinx system generator.
411-419
Electronic Edition (link) BibTeX
Volume 29,
Number 10,
December 2005
Copyright © Sun May 17 00:13:12 2009
by Michael Ley (ley@uni-trier.de)
