ARC 2007:
Mangaratiba,
Brazil
Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, João M. P. Cardoso (Eds.):
Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007.
Lecture Notes in Computer Science 4419 Springer 2007, ISBN 978-3-540-71430-9 BibTeX
Architectures [Regular Papers]
- Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev:
Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array.
1-13
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- Mazen A. R. Saghir, Rawan Naous:
A Configurable Multi-ported Register File Architecture for Soft Processor Cores.
14-25
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- Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic:
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture.
26-38
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- Je-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho:
Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture.
39-48
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- Jae Young Hur, Stephan Wong, Stamatis Vassiliadis:
Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs.
49-60
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- Jae Young Hur, Todor Stefanov, Stephan Wong, Stamatis Vassiliadis:
Systematic Customization of On-Chip Crossbar Interconnects.
61-72
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- Saar Drimer:
Authentication of FPGA Bitstreams: Why and How.
73-84
Electronic Edition (link) BibTeX
Architectures [Short Papers]
Mapping Techniques and Tools [Regular Papers]
- Joonseok Park, Pedro C. Diniz:
Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations.
97-109
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- Yazhuo Dong, Yong Dou, Jie Zhou:
Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware.
110-121
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- Rainer Scholz:
Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations.
122-129
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- Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis:
A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions.
130-141
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- Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi:
Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping.
142-154
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- Yong Dou, Jinhui Xu, Guiming Wu:
The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining.
155-166
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- Cesar Torres-Huitzil, Bernard Girau, Adrien Gauffriau:
Hardware/Software Codesign for Embedded Implementation of Neural Networks.
167-178
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- João Bispo, Ioannis Sourdis, João M. P. Cardoso, Stamatis Vassiliadis:
Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues.
179-190
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Mapping Techniques and Tools [Short Papers]
Arithmetic [Regular Papers]
- Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena:
Switching Activity Models for Power Estimation in FPGA Multipliers.
201-213
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- Jean-Luc Beuchat, Takanori Miyoshi, Yoshihito Oyama, Eiji Okamoto:
Multiplication over Fpm on FPGA: A Survey.
214-225
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- Francisco Rodríguez-Henríquez, Guillermo Morales-Luna, Nazar A. Saqib, Nareli Cruz Cortés:
A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm.
226-237
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- Edgar Ferrer, Dorothy Bollman, Oscar Moreno:
A Fast Finite Field Multiplier.
238-246
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Applications [Regular Papers]
- Rayan Chikhi, Steven Derrien, Auguste Noumsi, Patrice Quinton:
Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval.
247-258
Electronic Edition (link) BibTeX
- Javier Díaz, Eduardo Ros, Sonia Mota, Richard R. Carrillo:
Image Processing Architecture for Local Features Computation.
259-270
Electronic Edition (link) BibTeX
- Günter Knittel:
A Compact Shader for FPGA-Based Volume Rendering Accelerators.
271-282
Electronic Edition (link) BibTeX
- Yong-Min Lee, Chang-Seok Choi, Seung-Gon Hwang, Hyun Dong Kim, Chul Hong Min, Jae-Hyun Park, Hanho Lee, Tae-Seon Kim, Chong Ho Lee:
Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications.
283-292
Electronic Edition (link) BibTeX
- Xiaodong Yang, Shengmei Mou, Yong Dou:
FPGA-Accelerated Molecular Dynamics Simulations: An Overview.
293-301
Electronic Edition (link) BibTeX
- David B. Thomas, Wayne Luk, Michael Stumpf:
Reconfigurable Hardware Acceleration of Canonical Graph Labelling.
302-313
Electronic Edition (link) BibTeX
- Nilton B. Armstrong, Heitor S. Lopes, Carlos R. Erig Lima:
Reconfigurable Computing for Accelerating Protein Folding Simulations.
314-325
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- Edson P. Ferlin, Heitor S. Lopes, Carlos R. Erig Lima, Ederson Cichaczewski:
Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits.
326-336
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Applications [Short Papers]
- Sonia Mota, Eduardo Ros, Javier Díaz, Rafael Rodríguez-Gomez, Richard R. Carrillo:
A Space Variant Mapping Architecture for Reliable Car Segmentation.
337-342
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- Shinya Hiramoto, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads.
343-349
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- Séamas McGettrick, Dermot Geraghty, Ciarán McElroy:
Searching the Web with an FPGA Based Search Engine.
350-357
Electronic Edition (link) BibTeX
- Yoshiki Yamaguchi, Kenji Kanazawa, Yoshiharu Ohke, Tsutomu Maruyama:
An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemma.
358-364
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- Matteo Tomasi, Javier Díaz, Eduardo Ros:
Real Time Architectures for Moving-Objects Tracking.
365-372
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- Patrick Rocke, Brian McGinley, Fearghal Morgan, John Maher:
Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller.
373-378
Electronic Edition (link) BibTeX
- Carlos R. Erig Lima, Heitor S. Lopes, Maiko R. Moroz, Ramon M. Menezes:
Multiple Sequence Alignment Using Reconfigurable Computing.
379-384
Electronic Edition (link) BibTeX
- Wagner R. Weinert, César Benitez, Heitor S. Lopes, Carlos R. Erig Lima:
Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing.
385-390
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Copyright © Sat May 16 22:58:26 2009
by Michael Ley (ley@uni-trier.de)
