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Michael K. Birbas

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2008
9EENikos Petrellis, Fotios Gioulekas, Michael K. Birbas, John C. Kikidis, Alexios N. Birbas: Use of interleaving and error correction to infrared patterns for the improvement of position estimation systems. ETFA 2008: 488-491
2005
8EEFotios Gioulekas, Michael K. Birbas, Nikos S. Voros, George Kouklaras, Alexios N. Birbas: Heterogeneous system level co-simulation for the design of telecommunication systems. Journal of Systems Architecture 51(12): 688-705 (2005)
2004
7EEFotios Gioulekas, Michael K. Birbas, Nikos S. Voros, George Kouklaras, Alexios N. Birbas: A Heterogeneous Co-simulation Environment for Complex Embedded Telecommunication Systems. FDL 2004: 355-366
2001
6EEEvaggelinos P. Mariatos, Alexios N. Birbas, Michael K. Birbas: A mapping algorithm for computer-assisted exploration in the design of embedded systems. ACM Trans. Design Autom. Electr. Syst. 6(1): 122-147 (2001)
1998
5 Nikos S. Voros, S. Tsasakou, C. Valderrama, S. Arab, Alexios N. Birbas, Michael K. Birbas, Evaggelinos P. Mariatos, A. Andritsou: Hardware - Software Co-design of embedded telecommunication systems using multiple formalisms for application development. FORTE 1998: 387-403
4EENikos S. Voros, Evaggelinos P. Mariatos, Michael K. Birbas, Alexios N. Birbas, Nikos Petrellis, Spyrogiannis Batistatos: Reusable Architecture Templates and Automatic Specification Mapping for the Efficient Implementation of ATM Protocols. International Workshop on Rapid System Prototyping 1998: 45-50
1994
3 John Ant. Hallas, Evaggelinos P. Mariatos, Michael K. Birbas, Alexios N. Birbas, Constantinos E. Goutis: A CAD Tool for the Development of an Extra-Fast Fuzzy Logic Controller Based on FPGAs and Memory Modules. FPL 1994: 309-311
2 John Ant. Hallas, Michael K. Birbas, Alexios N. Birbas, John C. Kikidis, Constantinos E. Goutis: Near-Lossless Compression of Continuous-Tone Still Images Using Fuzzy Logic Notions and the Binary Arithmetic Coder (Q-Coder). ISCAS 1994: 125-128
1991
1 Dimitrios Soudris, Michael K. Birbas, Constantinos E. Goutis: Direct mapping of nested loops on piecewise regular processor arrays. Algorithms and Parallel VLSI Architectures 1991: 145-150

Coauthor Index

1A. Andritsou [5]
2S. Arab [5]
3Spyrogiannis Batistatos [4]
4Alexios N. Birbas [2] [3] [4] [5] [6] [7] [8] [9]
5Fotios Gioulekas [7] [8] [9]
6Constantinos E. Goutis (Costas E. Goutis) [1] [2] [3]
7John Ant. Hallas [2] [3]
8John C. Kikidis [2] [9]
9George Kouklaras [7] [8]
10Evaggelinos P. Mariatos [3] [4] [5] [6]
11Nikos Petrellis [4] [9]
12Dimitrios Soudris (D. J. Soudris) [1]
13S. Tsasakou [5]
14C. Valderrama [5]
15Nikos S. Voros [4] [5] [7] [8]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)