| 2004 |
|---|
| 4 | | Lily Huang,
Tai-Ying Jiang,
Jing-Yang Jou,
Heng-Liang Huang:
An efficient logic extraction algorithm using partitioning and circuit encoding.
ISCAS (5) 2004: 249-252 |
| 2002 |
|---|
| 3 | EE | Heng-Liang Huang,
Jing-Yang Jou:
Bootstrap Monte Carlo with Adaptive Stratification for Power Estimation.
Journal of Circuits, Systems, and Computers 11(4): 333-350 (2002) |
| 2001 |
|---|
| 2 | EE | Heng-Liang Huang,
Yeong-Ren Chen,
Jing-Yang Jou,
Wen-Zen Shen:
Grouped input power sensitive transition an input sequence compaction technique for power estimation.
ISCAS (5) 2001: 471-474 |
| 2000 |
|---|
| 1 | EE | Heng-Liang Huang,
Jiing-Yuan Lin,
Wen-Zen Shen,
Jing-Yang Jou:
A new method for constructing IP level power model based on power sensitivity.
ASP-DAC 2000: 135-140 |
