| 2005 |
|---|
| 5 | EE | Kai-Hui Chang,
Jeh-Yen Kang,
Han-Wei Wang,
Wei-Ting Tu,
Yi-Jong Yeh,
Sy-Yen Kuo:
Automatic Partitioner for Behavior Level Distributed Logic Simulation.
FORTE 2005: 525-528 |
| 2004 |
|---|
| 4 | EE | Kai-Hui Chang,
Wei-Ting Tu,
Yi-Jong Yeh,
Sy-Yen Kuo:
A Temporal Assertion Extension to Verilog.
ATVA 2004: 499-504 |
| 2002 |
|---|
| 3 | EE | Yi-Jong Yeh,
Sy-Yen Kuo:
An Optimization-Based Multiple-Voltage Scaling Technique for Low-Power CMOS Digital Design.
Journal of Circuits, Systems, and Computers 11(4): 365-376 (2002) |
| 2001 |
|---|
| 2 | EE | Yi-Jong Yeh,
Sy-Yen Kuo:
An optimization-based low-power voltage scaling technique using multiple supply voltages.
ISCAS (5) 2001: 535-538 |
| 1 | EE | Yi-Jong Yeh,
Sy-Yen Kuo,
Jing-Yang Jou:
Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 172-176 (2001) |
