| 1989 |
|---|
| 7 | EE | Hi-Keung Tony Ma,
Srinivas Devadas,
Ruey-Sing Wei,
Alberto L. Sangiovanni-Vincentelli:
Logic verification algorithms and their parallel implementation.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(2): 181-189 (1989) |
| 1988 |
|---|
| 6 | EE | Ruey-Sing Wei,
Steven G. Rothweiler,
Jing-Yang Jou:
BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping.
DAC 1988: 409-414 |
| 5 | EE | Chia-Jeng Tseng,
Ruey-Sing Wei,
Steven G. Rothweiler,
Michael M. Tong,
Ajoy K. Bose:
Bridge: A Versatile Behavioral Synthesis System.
DAC 1988: 415-420 |
| 1986 |
|---|
| 4 | | Ruey-Sing Wei,
Alberto L. Sangiovanni-Vincentelli:
New Front-End and Line Justification Algorithm for Automatic Test Generation.
ITC 1986: 121-128 |
| 3 | | Alberto L. Sangiovanni-Vincentelli,
Ruey-Sing Wei:
PROTEUS : A Logic Verification System for Combinational Circuits.
ITC 1986: 350-359 |
| 2 | EE | Ruey-Sing Wei,
Alberto L. Sangiovanni-Vincentelli:
PLATYPUS: A PLA Test Pattern Generation Tool.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 633-644 (1986) |
| 1985 |
|---|
| 1 | EE | Ruey-Sing Wei,
Alberto L. Sangiovanni-Vincentelli:
PLATYPUS: a PLA test pattern generation tool.
DAC 1985: 197-203 |
