| 2005 |
|---|
| 3 | EE | Yen-Fong Lee,
Shi-Yu Huang,
Sheng-Yu Hsu,
I-Ling Chen,
Cheng-Tao Shieh,
Jian-Cheng Lin,
Shih-Chieh Chang:
Power estimation starategies for a low-power security processor.
ASP-DAC 2005: 367-371 |
| 2003 |
|---|
| 2 | EE | Chien-Nan Jimmy Liu,
I-Ling Chen,
Jing-Yang Jou:
A Design-for-Verification Technique for Functional Pattern Reduction.
IEEE Design & Test of Computers 20(2): 48-55 (2003) |
| 2001 |
|---|
| 1 | EE | Chien-Nan Jimmy Liu,
I-Ling Chen,
Jing-Yang Jou:
An efficient design-for-verification technique for HDLs.
ASP-DAC 2001: 103-108 |
