Volume 14,
Number 1,
March 1998
Special Issue On Compiler Techniques For High-Performance Computing
- Jing-Chiou Liou, Michael A. Palis:
On the Effectiveness of Compiler-Time Scheduling Approaches for Distributed Memory Multiprocessor.
7-26
Electronic Edition (link) BibTeX
- S. K. S. Gupta, S. Drishnamurthy:
An Interprocedural Framework for Determining Efficient Array Data Redistributeions.
27-51
Electronic Edition (link) BibTeX
- Chien-Min Wang, Yomin Hou, Chiu-Yu Ku:
Compiler Techniques for Minimizing Link Contention of Linear-Constant Communication on k-ary n-cubes.
53-78
Electronic Edition (link) BibTeX
- Pangfeng Liu, Jan-Jan Wu:
Supporting Efficieent Tree Structures for Distributed Scientific Computation.
79-105
Electronic Edition (link) BibTeX
- Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Meenakshi A. Kandaswamy:
Locality Optimization Algorithms for Compilation of Out-of-Core Codes.
107-138
Electronic Edition (link) BibTeX
- Yin-Tsung Hwang, Jer-Sho Hwang:
Simulated Evolution Based Parallel Code Generation for Programmable DSP Processors.
139-165
Electronic Edition (link) BibTeX
- Frederic Desprez, Jack Dongarra, Fabrice Rastello, Yves Robert:
Determining the Idle Time of a Tiling: New Results.
167-190
Electronic Edition (link) BibTeX
- Beniamino Di Martino:
Algorithmic Concept Recognition Support for Automatic Parallelization: A Case Study on Loop Optimization and Parallelization.
191-203
Electronic Edition (link) BibTeX
- Jenn-Yuan Tsai, Zhenzhen Jiang, Zhiyuan Li, David J. Lilja, Xin Wang, Pen-Chung Yew, Bixia Zheng, Stephen J. Schwinn:
Integrating Parallelizing Compilation Technology and Processor Architecture for Cost-Effective Concurrent multithreading.
205-222
Electronic Edition (link) BibTeX
- Sangho Ha, Heunghwan Kim:
KU-Loop Scheme: An Efficient Loop Unfolding Scheme for Multithreaded Computation.
223-236
Electronic Edition (link) BibTeX
- Chao-Tung Yang, Shian-Shyong Tseng, Ming-Huei Hsieh, Shih-Hung Kao:
Efficient Run-Time Parallelization for DO Loops.
237-253
Electronic Edition (link) BibTeX
- Tsung-Chuan Huang, Po-Hsueh Hsu, Tze-Nan Sheng:
Efficient Run-Time Scheduling for Parallelizing Partially Parallel Loops.
255-264
Electronic Edition (link) BibTeX
- Fermín Sánchez, Jordi Cortadella:
Reducing Register Pressure in Software Pipelining.
265-279
Electronic Edition (link) BibTeX
- Sheng-De Wang, Wei-Der Jwo:
Replication and Partitioning for Data Arrays in Distributed Memory Systems.
281-298
Electronic Edition (link) BibTeX
Volume 14,
Number 2,
June 1998
Special Section On Artificial Intelligence
Regular Section Computer Networks
Graph Theory
Graphics
Pattern Recognition
Computer Architecture
Volume 14,
Number 3,
September 1998
Special Issue On Hardware Description Languages
Regular Section
VLSI Aid Design
Volume 14,
Number 4,
December 1998
Special Section On Parallel Processing
Regular Sections Computer Architecture
Neural Networks
VLSI Computer Aids Design Engineering
Distribution Programming
Copyright © Sun May 17 00:10:00 2009
by Michael Ley (ley@uni-trier.de)
