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Zhong-Fang Jin

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2002
2EEZhong-Fang Jin, J.-J. Laurin, Yvon Savaria: A practical approach to model long MIS interconnects in VLSI circuits. IEEE Trans. VLSI Syst. 10(4): 494-507 (2002)
1999
1EEZhong-Fang Jin, J.-J. Laurin, Yvon Savaria, P. Garon: A new approach to analyze interconnect delays in RC wire models. ISCAS (6) 1999: 246-249

Coauthor Index

1P. Garon [1]
2J.-J. Laurin [1] [2]
3Yvon Savaria [1] [2]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)