2002 | ||
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3 | EE | Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, S. Nishi, Y. Kubota, Isao Shirakawa, S. Imai: Parasitic capacitance modeling for multilevel interconnects. APCCAS (1) 2002: 59-64 |
1999 | ||
2 | EE | Y. Sugimoto, S. Imai: The design of a 1 V, 40 MHz, current-mode sample-and-hold circuit with 10-bit linearity. ISCAS (2) 1999: 132-135 |
1 | EE | T. Yamada, S. Imai, S. Ueno: On VLSI decompositions for deBruijn graphs. ISCAS (6) 1999: 165-169 |
1 | Makoto Furuie | [3] |
2 | Y. Kubota | [3] |
3 | BuYeol Lee | [3] |
4 | S. Nishi | [3] |
5 | Isao Shirakawa | [3] |
6 | Y. Sugimoto | [2] |
7 | Sadahiro Tani | [3] |
8 | Shuji Tsukiyama | [3] |
9 | Yoshihiro Uchida | [3] |
10 | S. Ueno | [1] |
11 | T. Yamada | [1] |