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Wei Wang

Purdue University Indianapolis

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2005
8EEShaoqiang Bi, Warren J. Gross, Wei Wang, Asim J. Al-Khalili, M. N. S. Swamy: An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction. IWSOC 2005: 396-399
7EEWei Wang, Xiaolin Zhang, Chenyang Yang, M. N. S. Swamy, M. Omair Ahmad: RRNS Quasi-Chaotic Coding and Its FPGA Implementation. SNPD 2005: 274-280
2004
6 Shaoqiang Bi, Wei Wang, Asim J. Al-Khalili: Modulo deflation in (2n+1, 2n, 2n-1) converters. ISCAS (2) 2004: 429-432
5EEWei Wang, M. N. S. Swamy, M. Omair Ahmad: RNS Application for Digital Image Processing. IWSOC 2004: 77-80
4EEWei Wang, M. N. S. Swamy, M. Omair Ahmad: Novel Design and Fpga Implementation of Da-rns Fir Filters. Journal of Circuits, Systems, and Computers 13(6): 1233-1250 (2004)
2003
3EEWei Wang, M. N. S. Swamy, M. Omair Ahmad: Moduli selection in RNS for efficient VLSI implementation. ISCAS (4) 2003: 512-515
2002
2EEWei Wang, M. N. S. Swamy, M. Omair Ahmad: A new architecture of RRNS error-correcting QC encoder/decoder and its FPGA implementation. ISCAS (5) 2002: 813-816
1999
1EEWei Wang, M. N. S. Swamy, M. Omair Ahmad, Yuke Wang: A high-speed residue-to-binary converter and a scheme for its VLSI implementation. ISCAS (6) 1999: 330-333

Coauthor Index

1M. Omair Ahmad [1] [2] [3] [4] [5] [7]
2Asim J. Al-Khalili (A. J. Al-Khalili) [6] [8]
3Shaoqiang Bi [6] [8]
4Warren J. Gross [8]
5M. N. S. Swamy [1] [2] [3] [4] [5] [7] [8]
6Yuke Wang [1]
7Chenyang Yang [7]
8Xiaolin Zhang [7]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)