| 2002 |
|---|
| 8 | EE | S. Tantry,
T. Oura,
T. Yoneyama,
H. Asai:
A low voltage floating resistor having positive and negative resistance values.
APCCAS (1) 2002: 347-350 |
| 7 | EE | T. Oura,
T. Yoneyama,
S. Tantry,
H. Asai:
A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values.
ISCAS (3) 2002: 739-742 |
| 6 | EE | I. Hattori,
A. Kamo,
T. Watanabe,
H. Asai:
Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method.
ISCAS (5) 2002: 29-32 |
| 5 | EE | H. Kubota,
A. Kamo,
T. Watanabe,
H. Asai:
Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique.
ISCAS (5) 2002: 649-552 |
| 2001 |
|---|
| 4 | EE | S. Tantry,
T. Yoneyama,
H. Asai:
Two floating resistor circuits and their applications to synaptic weights in analog neural networks.
ISCAS (1) 2001: 564-567 |
| 1999 |
|---|
| 3 | EE | T. Watanabe,
H. Asai:
Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method.
ISCAS (6) 1999: 266-269 |
| 2 | EE | A. Kamo,
T. Watanabe,
H. Asai:
Expanded GMC for transient analysis of transmission line networks.
ISCAS (6) 1999: 33-36 |
| 1975 |
|---|
| 1 | | H. Asai,
S. C. Lee:
Design of Queuing Buffer Register Size.
Inf. Process. Lett. 3(5): 147-152 (1975) |
