| 2007 |
|---|
| 11 | EE | Richard Ruzicka,
Josef Strnadel:
Test Controller Synthesis Constrained by Circuit Testability Analysis.
DSD 2007: 626-633 |
| 2006 |
|---|
| 10 | | Josef Strnadel:
Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-Space.
DDECS 2006: 161-162 |
| 9 | EE | Tomas Pecenka,
Josef Strnadel,
Zdenek Kotásek,
Lukás Sekanina:
Testability Estimation Based on Controllability and Observability Parameters.
DSD 2006: 504-514 |
| 8 | EE | Josef Strnadel,
Arghya Kumar Dhali:
Novel Optimizing Approach in the Area of STEP-Based Construction of Sessionless, Power-Constrainted, TAM and Time Optimal Test Schedules.
ECBS 2006: 360-367 |
| 7 | EE | Josef Strnadel,
Zdenek Kotásek:
SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System.
ECBS 2006: 497-498 |
| 6 | | Josef Strnadel:
Testability Analysis and Improvements of Register-Transfer Level Digital Circuits.
Computers and Artificial Intelligence 25(5): (2006) |
| 2005 |
|---|
| 5 | EE | Josef Strnadel,
Zdenek Kotásek:
Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies.
DSD 2005: 420-427 |
| 4 | EE | Tomas Pecenka,
Zdenek Kotásek,
Lukás Sekanina,
Josef Strnadel:
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties.
Evolvable Hardware 2005: 51-58 |
| 2004 |
|---|
| 3 | | Daniel Mika,
Josef Strnadel,
Kotásek Zdenik:
The Identification of registers in RTL Structures for the Test Application.
ISoLA (Preliminary proceedings) 2004: 317-319 |
| 2003 |
|---|
| 2 | EE | Zdenek Kotásek,
Daniel Mika,
Josef Strnadel:
Test scheduling for embedded systems.
DSD 2003: 463-467 |
| 2002 |
|---|
| 1 | EE | Josef Strnadel,
Zdenek Kotásek:
Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level.
DSD 2002: 166-173 |
