Adam Milik

2008
4	EE	Andrzej Pulka, Adam Milik: VEST - An Intelligent Tool for Timing SoCs Verification Using UML Timing Diagrams. FDL 2008: 118-123
2007
3	EE	Adam Milik, Andrzej Pulka: Common HDL-Matlab Simulation Environment. FDL 2007: 68-73
2005
2	EE	Dariusz Kania, Józef Kulisz, Adam Milik: A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. DSD 2005: 114-121
1	EE	Dariusz Kania, Adam Milik, Józef Kulisz: Decomposition of Multi-Output Functions for CPLDs. DSD 2005: 442-449

Coauthor Index

1	Dariusz Kania	[1] [2]
2	Józef Kulisz	[1] [2]
3	Andrzej Pulka	[3] [4]

Colors in the list of coauthors