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Adam Milik

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2008
4EEAndrzej Pulka, Adam Milik: VEST - An Intelligent Tool for Timing SoCs Verification Using UML Timing Diagrams. FDL 2008: 118-123
2007
3EEAdam Milik, Andrzej Pulka: Common HDL-Matlab Simulation Environment. FDL 2007: 68-73
2005
2EEDariusz Kania, Józef Kulisz, Adam Milik: A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. DSD 2005: 114-121
1EEDariusz Kania, Adam Milik, Józef Kulisz: Decomposition of Multi-Output Functions for CPLDs. DSD 2005: 442-449

Coauthor Index

1Dariusz Kania [1] [2]
2Józef Kulisz [1] [2]
3Andrzej Pulka [3] [4]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)