| |
| 2008 | ||
|---|---|---|
| 3 | EE | Lukás Starecek, Lukás Sekanina, Zdenek Kotásek: Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. DDECS 2008: 255-268 |
| 2006 | ||
| 2 | EE | Lukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek: Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. AHS 2006: 186-193 |
| 1 | Lukás Sekanina, Lukás Starecek, Zdenek Kotásek: Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. DDECS 2006: 85-86 | |
| 1 | Zbysek Gajda | [2] |
| 2 | Zdenek Kotásek | [1] [2] [3] |
| 3 | Lukás Sekanina | [1] [2] [3] |