| |
| 2008 | ||
|---|---|---|
| 5 | EE | Daesun Oh, Keshab K. Parhi: Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes. ACM Great Lakes Symposium on VLSI 2008: 451-456 |
| 4 | EE | Daesun Oh, Keshab K. Parhi: Area efficient controller design of barrel shifters for reconfigurable LDPC decoders. ISCAS 2008: 240-243 |
| 2007 | ||
| 3 | EE | Daesun Oh, Keshab K. Parhi: Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes. ISCAS 2007: 1855-1858 |
| 2 | EE | Daesun Oh, Keshab K. Parhi: Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC Codes. ISCAS 2007: 2758-2761 |
| 2006 | ||
| 1 | EE | Daesun Oh, Keshab K. Parhi: Low Complexity Design of High Speed Parallel Decision Feedback Equalizers. ASAP 2006: 118-124 |
| 1 | Keshab K. Parhi | [1] [2] [3] [4] [5] |