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Po-Hsien Chang

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2008
1EEYu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang: Synthesis of a novel timing-error detection architecture. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008)

Coauthor Index

1Shih-Chieh Chang [1]
2TingTing Hwang [1]
3Yu-Shih Su [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)