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Stefan Mangard

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2009
23EEThomas Popp, Mario Kirschbaum, Stefan Mangard: Practical Attacks on Masked Hardware. CT-RSA 2009: 211-225
2007
22EEStefan Tillich, Christoph Herbst, Stefan Mangard: Protecting AES Software Implementations on 32-Bit Processors Against Power Analysis. ACNS 2007: 141-157
21EEMichael Hutter, Stefan Mangard, Martin Feldhofer: Power and EM Attacks on Passive 13.56 MHz RFID Devices. CHES 2007: 320-333
20EEThomas Popp, Mario Kirschbaum, Thomas Zefferer, Stefan Mangard: Evaluation of the Masked Logic Style MDPL on a Prototype Chip. CHES 2007: 81-94
19EEElisabeth Oswald, Stefan Mangard: Template Attacks on Masking - Resistance Is Futile. CT-RSA 2007: 243-256
18EESrivaths Ravi, Stefan Mangard: Tutorial T1: Designing Secure SoCs. VLSI Design 2007: 3
17EEThomas Popp, Stefan Mangard, Elisabeth Oswald: Power Analysis Attacks and Countermeasures. IEEE Design & Test of Computers 24(6): 535-543 (2007)
2006
16EEChristoph Herbst, Elisabeth Oswald, Stefan Mangard: An AES Smart Card Implementation Resistant to Power Analysis Attacks. ACNS 2006: 239-252
15EEStefan Mangard, Kai Schramm: Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations. CHES 2006: 76-90
14EEElisabeth Oswald, Stefan Mangard, Christoph Herbst, Stefan Tillich: Practical Second-Order DPA Attacks for Masked Smart Card Implementations of Block Ciphers. CT-RSA 2006: 192-207
13EEThomas Popp, Stefan Mangard: Implementation aspects of the DPA-resistant logic style MDPL. ISCAS 2006
12EEManfred Josef Aigner, Stefan Mangard, Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Thomas Popp, Giuseppe Scotti, Alessandro Trifiletti: Side channel analysis resistant design flow. ISCAS 2006
11EEHyungSo Yoo, Christoph Herbst, Stefan Mangard, Elisabeth Oswald, Sang-Jae Moon: Investigations of Power Analysis Attacks and Countermeasures for ARIA. WISA 2006: 160-172
2005
10EEStefan Mangard, Norbert Pramstaller, Elisabeth Oswald: Successfully Attacking Masked AES Hardware Implementations. CHES 2005: 157-171
9EEThomas Popp, Stefan Mangard: Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints. CHES 2005: 172-186
8EEStefan Mangard, Thomas Popp, Berndt M. Gammel: Side-Channel Leakage of Masked CMOS Gates. CT-RSA 2005: 351-365
7EEElisabeth Oswald, Stefan Mangard, Norbert Pramstaller, Vincent Rijmen: A Side-Channel Analysis Resistant Description of the AES S-Box. FSE 2005: 413-423
6EEManfred Josef Aigner, Stefan Mangard, Renato Menicocci, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti: A novel CMOS logic style with data independent power consumption. ISCAS (2) 2005: 1066-1069
2004
5EENorbert Pramstaller, Stefan Mangard, Sandra Dominikus, Johannes Wolkerstorfer: Efficient AES Implementations on ASICs and FPGAs. AES Conference 2004: 98-112
4EEStefan Mangard: Hardware Countermeasures against DPA ? A Statistical Analysis of Their Effectiveness. CT-RSA 2004: 222-235
2003
3EEStefan Mangard, Manfred Josef Aigner, Sandra Dominikus: A Highly Regular and Scalable AES Hardware Architecture. IEEE Trans. Computers 52(4): 483-491 (2003)
2002
2EEStefan Mangard: A Simple Power-Analysis (SPA) Attackon Implementations of the AES Key Expansion. ICISC 2002: 343-358
2001
1EEGiuseppe Ateniese, Stefan Mangard: A new approach to DNS security (DNSSEC). ACM Conference on Computer and Communications Security 2001: 86-95

Coauthor Index

1Manfred Josef Aigner [3] [6] [12]
2Giuseppe Ateniese [1]
3Sandra Dominikus [3] [5]
4Martin Feldhofer [21]
5Berndt M. Gammel [8]
6Christoph Herbst [11] [14] [16] [22]
7Michael Hutter [21]
8Mario Kirschbaum [20] [23]
9Francesco Menichelli [12]
10Renato Menicocci [6] [12]
11Sang-Jae Moon [11]
12Mauro Olivieri [6] [12]
13Elisabeth Oswald [7] [10] [11] [14] [16] [17] [19]
14Thomas Popp [8] [9] [12] [13] [17] [20] [23]
15Norbert Pramstaller [5] [7] [10]
16Srivaths Ravi [18]
17Vincent Rijmen [7]
18Kai Schramm [15]
19Giuseppe Scotti [6] [12]
20Stefan Tillich [14] [22]
21Alessandro Trifiletti [6] [12]
22Johannes Wolkerstorfer [5]
23HyungSo Yoo [11]
24Thomas Zefferer [20]

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Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)