2009 |
23 | EE | Thomas Popp,
Mario Kirschbaum,
Stefan Mangard:
Practical Attacks on Masked Hardware.
CT-RSA 2009: 211-225 |
2007 |
22 | EE | Stefan Tillich,
Christoph Herbst,
Stefan Mangard:
Protecting AES Software Implementations on 32-Bit Processors Against Power Analysis.
ACNS 2007: 141-157 |
21 | EE | Michael Hutter,
Stefan Mangard,
Martin Feldhofer:
Power and EM Attacks on Passive 13.56 MHz RFID Devices.
CHES 2007: 320-333 |
20 | EE | Thomas Popp,
Mario Kirschbaum,
Thomas Zefferer,
Stefan Mangard:
Evaluation of the Masked Logic Style MDPL on a Prototype Chip.
CHES 2007: 81-94 |
19 | EE | Elisabeth Oswald,
Stefan Mangard:
Template Attacks on Masking - Resistance Is Futile.
CT-RSA 2007: 243-256 |
18 | EE | Srivaths Ravi,
Stefan Mangard:
Tutorial T1: Designing Secure SoCs.
VLSI Design 2007: 3 |
17 | EE | Thomas Popp,
Stefan Mangard,
Elisabeth Oswald:
Power Analysis Attacks and Countermeasures.
IEEE Design & Test of Computers 24(6): 535-543 (2007) |
2006 |
16 | EE | Christoph Herbst,
Elisabeth Oswald,
Stefan Mangard:
An AES Smart Card Implementation Resistant to Power Analysis Attacks.
ACNS 2006: 239-252 |
15 | EE | Stefan Mangard,
Kai Schramm:
Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations.
CHES 2006: 76-90 |
14 | EE | Elisabeth Oswald,
Stefan Mangard,
Christoph Herbst,
Stefan Tillich:
Practical Second-Order DPA Attacks for Masked Smart Card Implementations of Block Ciphers.
CT-RSA 2006: 192-207 |
13 | EE | Thomas Popp,
Stefan Mangard:
Implementation aspects of the DPA-resistant logic style MDPL.
ISCAS 2006 |
12 | EE | Manfred Josef Aigner,
Stefan Mangard,
Francesco Menichelli,
Renato Menicocci,
Mauro Olivieri,
Thomas Popp,
Giuseppe Scotti,
Alessandro Trifiletti:
Side channel analysis resistant design flow.
ISCAS 2006 |
11 | EE | HyungSo Yoo,
Christoph Herbst,
Stefan Mangard,
Elisabeth Oswald,
Sang-Jae Moon:
Investigations of Power Analysis Attacks and Countermeasures for ARIA.
WISA 2006: 160-172 |
2005 |
10 | EE | Stefan Mangard,
Norbert Pramstaller,
Elisabeth Oswald:
Successfully Attacking Masked AES Hardware Implementations.
CHES 2005: 157-171 |
9 | EE | Thomas Popp,
Stefan Mangard:
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints.
CHES 2005: 172-186 |
8 | EE | Stefan Mangard,
Thomas Popp,
Berndt M. Gammel:
Side-Channel Leakage of Masked CMOS Gates.
CT-RSA 2005: 351-365 |
7 | EE | Elisabeth Oswald,
Stefan Mangard,
Norbert Pramstaller,
Vincent Rijmen:
A Side-Channel Analysis Resistant Description of the AES S-Box.
FSE 2005: 413-423 |
6 | EE | Manfred Josef Aigner,
Stefan Mangard,
Renato Menicocci,
Mauro Olivieri,
Giuseppe Scotti,
Alessandro Trifiletti:
A novel CMOS logic style with data independent power consumption.
ISCAS (2) 2005: 1066-1069 |
2004 |
5 | EE | Norbert Pramstaller,
Stefan Mangard,
Sandra Dominikus,
Johannes Wolkerstorfer:
Efficient AES Implementations on ASICs and FPGAs.
AES Conference 2004: 98-112 |
4 | EE | Stefan Mangard:
Hardware Countermeasures against DPA ? A Statistical Analysis of Their Effectiveness.
CT-RSA 2004: 222-235 |
2003 |
3 | EE | Stefan Mangard,
Manfred Josef Aigner,
Sandra Dominikus:
A Highly Regular and Scalable AES Hardware Architecture.
IEEE Trans. Computers 52(4): 483-491 (2003) |
2002 |
2 | EE | Stefan Mangard:
A Simple Power-Analysis (SPA) Attackon Implementations of the AES Key Expansion.
ICISC 2002: 343-358 |
2001 |
1 | EE | Giuseppe Ateniese,
Stefan Mangard:
A new approach to DNS security (DNSSEC).
ACM Conference on Computer and Communications Security 2001: 86-95 |