| 2009 |
|---|
| 6 | EE | Balaji Vaidyanathan,
Anthony S. Oates,
Yuan Xie,
Yu Wang:
NBTI-aware statistical circuit delay assessment.
ISQED 2009: 13-18 |
| 2007 |
|---|
| 5 | EE | Balaji Vaidyanathan,
Wei-Lun Hung,
Feng Wang,
Yuan Xie,
Narayanan Vijaykrishnan,
Mary Jane Irwin:
Architecting Microprocessor Components in 3D Design Space.
VLSI Design 2007: 103-108 |
| 4 | EE | Feng Wang,
Yuan Xie,
R. Rajaraman,
Balaji Vaidyanathan:
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model.
VLSI Design 2007: 165-170 |
| 3 | EE | Liping Xue,
Mahmut T. Kandemir,
Guilin Chen,
Feihui Li,
Ozcan Ozturk,
R. Ramanarayanan,
Balaji Vaidyanathan:
Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors.
VLSI Design 2007: 251-258 |
| 2 | EE | Feihui Li,
Guilin Chen,
Mahmut T. Kandemir,
Ozcan Ozturk,
Mustafa Karaköy,
R. Ramanarayanan,
Balaji Vaidyanathan:
A Process Scheduler-Based Approach to NoC Power Management.
VLSI Design 2007: 77-82 |
| 2006 |
|---|
| 1 | EE | Balaji Vaidyanathan,
Suresh Srinivasan,
Yuan Xie,
Narayanan Vijaykrishnan,
Rong Luo:
Leakage Optimized DECAP Design for FPGAs.
APCCAS 2006: 960-963 |
