15. HPCA 2009:
Raleigh,
North Carolina,
USA
15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA.
IEEE Computer Society 2009 BibTeX
Keynote Session I
Best Paper Nominees
- Eiman Ebrahimi, Onur Mutlu, Yale N. Patt:
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems.
7-17
Electronic Edition (link) BibTeX
- Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. Holloway, Gu-Yeon Wei, Michael D. Smith, David Brooks:
Voltage emergency prediction: Using signatures to reduce operating margins.
18-29
Electronic Edition (link) BibTeX
- Yi Xu, Yu Du, Bo Zhao, Xiuyi Zhou, Youtao Zhang, Jun Yang:
A low-radix and low-diameter 3D interconnection network design.
30-42
Electronic Edition (link) BibTeX
Multicore Cache Architectures
Reliability
Panel
Keynote II
On-Chip Networks-I
Processor Microarchitecture-I
NUCA and 3D Stacked Memory Hierarchies
- Mainak Chaudhuri:
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches.
227-238
Electronic Edition (link) BibTeX
- Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen:
A novel architecture of the 3D stacked MRAM L2 cache for CMPs.
239-249
Electronic Edition (link) BibTeX
- Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John B. Carter:
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches.
250-261
Electronic Edition (link) BibTeX
- Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha Udipi, Rajeev Balasubramonian, Ravishankar Iyer, Srihari Makineni, Donald Newell:
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.
262-274
Electronic Edition (link) BibTeX
Power/Performance-Efficient Architectures and Accelerators
- Sami Yehia, Sylvain Girbal, Hugues Berry, Olivier Temam:
Reconciling specialization and flexibility through compound circuits.
277-288
Electronic Edition (link) BibTeX
- Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi:
CAMP: A technique to estimate per-structure power at run-time using a few simple parameters.
289-300
Electronic Edition (link) BibTeX
- Sebastian Herbert, Diana Marculescu:
Variation-aware dynamic voltage/frequency scaling.
301-312
Electronic Edition (link) BibTeX
- Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke:
Bridging the computation gap between programmable processors and hardwired accelerators.
313-322
Electronic Edition (link) BibTeX
Industrial Perspectives Panel
Performance Modeling and Analysis
On-Chip Networks-II
Security,
Verification,
and Validation
- Yunji Chen, Yi Lv, Weiwu Hu, Tianshi Chen, Haihua Shen, Pengyu Wang, Hong Pan:
Fast complete memory consistency verification.
381-392
Electronic Edition (link) BibTeX
- Jingfei Kong, Onur Aciiçmez, Jean-Pierre Seifert, Huiyang Zhou:
Hardware-software integrated approaches to defend against software cache-based side channel attacks.
393-404
Electronic Edition (link) BibTeX
- Andrew DeOrio, Ilya Wagner, Valeria Bertacco:
Dacota: Post-silicon validation of the memory subsystem in multi-core designs.
405-416
Electronic Edition (link) BibTeX
Processor Microarchitecture-II
Copyright © Sat May 16 23:14:58 2009
by Michael Ley (ley@uni-trier.de)
