4. IWSOC 2004:
Banff,
Alberta,
Canada
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 19-21 July 2004, Banff, Alberta, Canada.
IEEE Computer Society 2004, ISBN 0-7695-2182-7 BibTeX
Plenary Session
Tutorial 1
Tutorial 2
Tutorial 3
Sensor IP-Blocks
Modeling and Simulation I
Advanced Arithmetic IP-Blocks
Verification and Testing
Analog and Mixed Signal I
- D. Morin, F. Normandin, M.-E. Grandmaison, H. Dang, Yvon Savaria, Mohamad Sawan:
An Intellectual Property Module for Auto-Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters.
111-114
Electronic Edition (link) BibTeX
- Hung Tien Bui, Yvon Savaria:
10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS.
115-118
Electronic Edition (link) BibTeX
- R. Chebli, Mohamad Sawan:
A CMOS High-Voltage DC-DC Up Converter Dedicated for Ultrasonic Applications.
119-122
Electronic Edition (link) BibTeX
- Masud H. Chowdhury, Yehea I. Ismail:
Possible Noise Failure Modes in Static and Dynamic Circuits.
123-126
Electronic Edition (link) BibTeX
- Donghoon Han, Abhijit Chatterjee:
Simulation-in-the-Loop Analog Circuit Sizing Method using Adaptive Model-based Simulated Annealing.
127-130
Electronic Edition (link) BibTeX
- Y. Ibrahim, Graham A. Jullien, William C. Miller:
Ultra Low Noise Signed Digit Arithmetic using Cellular Neural Networks.
136-142
Electronic Edition (link) BibTeX
- Deng Lei, Wen Gao, Ming-Zeng Hu, Zhenzhou Ji:
An Efficient VLSI Implementation of MC Interpolation for MPEG-4.
149-152
Electronic Edition (link) BibTeX
- Ling-zhi Liu, Lin Qiu, Meng-tian Rong, Jiang Li:
A 2-D Forward/Inverse Integer Transform Processor of H.264 Based on Highly-parallel Architecture.
158-161
Electronic Edition (link) BibTeX
- Victor H. S. Ha, Sung Kyu Choi, Jong-Gu Jeon, Geon Hyoung Lee, Won-Kap Jang, Woo-Sung Shim:
Real-time Audio/Video Decoders for Digital Multimedia Broadcasting.
162-167
Electronic Edition (link) BibTeX
- Hongkyu Kim, D. Scott Wills, Linda M. Wills:
Empirical Analysis of Operand Usage and Transport in Multimedia Applications.
168-171
Electronic Edition (link) BibTeX
- Yung-Chi Chang, Chih-Wei Hsu, Liang-Gee Chen:
MPEG-4 FGS Encoder Design for an Interactive Content-aware MPEG-4 Video Streaming SOC.
172-175
Electronic Edition (link) BibTeX
Logic Synthesis
- Sherif G. Aly, Ashraf M. Salem:
Observability-Based RTL Simulation using JAVA.
179-182
Electronic Edition (link) BibTeX
- Jean-Pierre David, Etienne Bergeron:
A Step towards Intelligent Translation from High-Level Design to RTL.
183-188
Electronic Edition (link) BibTeX
- M. Watheq El-Kharashi, M. H. El-Malaki, S. Hammad, Ashraf Salem, A. Wahdan:
Towards Automating Hardware/Software Co-Design.
189-192
Electronic Edition (link) BibTeX
- Ashwin K. Kumaraswamy, Ahmet T. Erdogan, Indrajit Atluri:
Development of Timing Driven IP Design Flow based on Physical Knowledge Synthesis.
193-197
Electronic Edition (link) BibTeX
- Milan Pastrnak, Peter Poplavko, Peter H. N. de With, Dirk Farin:
Data-flow Timing Models of Dynamic Multimedia Applications for Multiprocessor Systems.
206-209
Electronic Edition (link) BibTeX
- Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Marek Syrzycki:
Design Strategies for ESD Protection in SOC.
210-214
Electronic Edition (link) BibTeX
- Mikael Olausson, Anders Edman, Dake Liu:
Bit Memory Instructions for a General CPU.
215-218
Electronic Edition (link) BibTeX
- Keh-Jeng Chang:
Accurate On-Chip Variation Modeling to Achieve Design for Manufacturability.
219-222
Electronic Edition (link) BibTeX
Analog and Mixed Signal II
OnChip Bus and Interconnect
- Mountassar Maamoun, Boualem Laichi, Abdelhalim Benbelkacem, Daoud Berkani:
Interfacing in Microprocessor-based Systems with an Advanced Physical Addressing.
243-246
Electronic Edition (link) BibTeX
- Krzysztof Iniewski, R. Badalone, M. Lapointe, Marek Syrzycki:
SERDES Technology for Gigabit I/O Communications in Storage Area Networking.
247-252
Electronic Edition (link) BibTeX
- Tina Lindkvist, Jacob Löfvenberg, Henrik Ohlsson, Kenny Johansson, Lars Wanhammar:
A Power-Efficient, Low-Complexity, Memoryless Coding Scheme for Buses with Dominating Inter-Wire Capacitances.
257-262
Electronic Edition (link) BibTeX
- Daniel Wiklund, Sumant Sathe, Dake Liu:
Network on Chip Simulations for Benchmarking.
269-274
Electronic Edition (link) BibTeX
- Jacob Löfvenberg:
Non-Redundant Coding for Deep Sub-Micron Address Buses.
275-279
Electronic Edition (link) BibTeX
- Azeddien M. Sllame:
A Model for a Reusable System-on-a-Chip Hardware Component Integrated with Design Exploration Methodology.
287-290
Electronic Edition (link) BibTeX
- Xizhi Li, Tiecai Li:
ECOMIPS: An Economic MIPS CPU Design on FPGA.
291-294
Electronic Edition (link) BibTeX
- S. A. Rahim, Laurence E. Turner:
A Field Programmable Bit-Serial Digital Signal Processor.
295-298
Electronic Edition (link) BibTeX
- Pascal Nsame, Yvon Savaria:
A Customizable Embedded SoC Platform Architecture.
299-304
Electronic Edition (link) BibTeX
SoC for Network and Communication Applications
Copyright © Sat May 16 23:27:29 2009
by Michael Ley (ley@uni-trier.de)
