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Alexander Zaslavsky

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2007
6EEKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. DATE 2007: 576-581
5EEKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Designing Nanoscale Logic Circuits Based on Markov Random Fields. J. Electronic Testing 23(2-3): 255-266 (2007)
2006
4EEKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Optimizing noise-immune nanoscale circuits using principles of Markov random fields. ACM Great Lakes Symposium on VLSI 2006: 149-152
3EEKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Designing MRF based error correcting circuits for memory elements. DATE 2006: 792-793
2EEKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. IEEE Micro 26(5): 19-27 (2006)
2005
1EEKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Designing logic circuits for probabilistic computation in the presence of noise. DAC 2005: 485-490

Coauthor Index

1R. Iris Bahar [1] [2] [3] [4] [5] [6]
2Joseph L. Mundy [1] [2] [3] [4] [5] [6]
3Kundan Nepal [1] [2] [3] [4] [5] [6]
4William R. Patterson [1] [2] [3] [4] [5] [6]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)