| |
| 2004 | ||
|---|---|---|
| 5 | EE | Laurent Arditi, Gérard Berry, Michael Kishinevsky: Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs. FMCAD 2004: 128-143 |
| 2001 | ||
| 4 | EE | Laurent Arditi, Hédi Boufaïed, Arnaud Cavanié, Vincent Stehlé: Coverage Directed Generation of System-Level Test Cases for the Validation of a DSP System. FME 2001: 449-464 |
| 1996 | ||
| 3 | Laurent Arditi: BMDs Can Delay the Use of Theorem Proving for Verifying Arithmetic Assembly Instructions. FMCAD 1996: 34-48 | |
| 1995 | ||
| 2 | EE | Laurent Arditi, Hélène Collavizza: An Object-Oriented Framework for the Formal Verification of Processors. ECOOP 1995: 215-234 |
| 1 | EE | Laurent Arditi, Hélène Collavizza: Towards verifying VHDL descriptions of processors. EURO-DAC 1995: 414-419 |
| 1 | Gérard Berry | [5] |
| 2 | Hédi Boufaïed | [4] |
| 3 | Arnaud Cavanié | [4] |
| 4 | Hélène Collavizza | [1] [2] |
| 5 | Michael Kishinevsky | [5] |
| 6 | Vincent Stehlé | [4] |