| 1995 |
|---|
| 4 | EE | Ronald Herrmann,
Thomas Reielts:
Verification of a production cell using an automatic verification environment for VHDL.
EURO-DAC 1995: 542-547 |
| 3 | | Gert Döhmen,
Ronald Herrmann,
Hergen Pargmann:
Translating VHDL into Functional Symbolic Finite-State Models.
Formal Methods in System Design 7(1/2): 125-148 (1995) |
| 1994 |
|---|
| 2 | | Dennis Dams,
Rob Gerth,
Gert Döhmen,
Ronald Herrmann,
Peter Kelb,
Hergen Pargmann:
Model Checking Using Adaptive State and Data Abstraction.
CAV 1994: 455-467 |
| 1 | EE | Ronald Herrmann,
Hergen Pargmann:
Computing binary decision diagrams for VHDL data types.
EURO-DAC 1994: 578-583 |
