| |
| 1996 | ||
|---|---|---|
| 3 | Vojin G. Oklobdzija, David Villeger, Simon S. Liu: A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach. IEEE Trans. Computers 45(3): 294-306 (1996) | |
| 1995 | ||
| 2 | EE | Vojin G. Oklobdzija, David Villeger: Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology. IEEE Trans. VLSI Syst. 3(2): 292-301 (1995) |
| 1994 | ||
| 1 | EE | Vojin G. Oklobdzija, David Villeger, Thierry Soulas: An integrated multiplier for complex numbers. VLSI Signal Processing 7(3): 213-222 (1994) |
| 1 | Simon S. Liu | [3] |
| 2 | Vojin G. Oklobdzija | [1] [2] [3] |
| 3 | Thierry Soulas | [1] |