| 2002 |
|---|
| 5 | EE | M. Olivieri:
Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design.
IEEE Trans. VLSI Syst. 10(5): 595-600 (2002) |
| 2001 |
|---|
| 4 | EE | M. Olivieri:
A genetic approach to the design space exploration of superscalar microprocessor architectures.
ISCAS (5) 2001: 69-72 |
| 3 | EE | M. Olivieri:
Design of synchronous and asynchronous variable-latency pipelined multipliers.
IEEE Trans. VLSI Syst. 9(2): 365-376 (2001) |
| 2 | EE | M. Olivieri:
Correction to "design of synchronous and asynchronous variable-latency pipelined multipliers".
IEEE Trans. VLSI Syst. 9(4): 558-559 (2001) |
| 1995 |
|---|
| 1 | EE | A. De Gloria,
M. Olivieri:
Efficient semicustom micropipeline design.
IEEE Trans. VLSI Syst. 3(3): 464-469 (1995) |
