R. Kalyanaraman

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1995

1 EE R. Vemuri, R. Kalyanaraman: Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming. IEEE Trans. VLSI Syst. 3(2): 201-214 (1995)

1995
1	EE	R. Vemuri, R. Kalyanaraman: Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming. IEEE Trans. VLSI Syst. 3(2): 201-214 (1995)

Coauthor Index

1 R. Vemuri [1]