14. FCCM 2006:
Napa,
CA,
USA
14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings.
IEEE Computer Society 2006, ISBN 0-7695-2661-6 BibTeX
Session 1:
Supercomputer Applications
Session 2:
Methodology and Tools
Session 3:
Data Generation and Processing
Session 4:
Hybrid Systems
Session 5:
Multi-processor/Threaded System
- Arun Patel, Christopher A. Madill, Manuel Saldaña, Chris Comis, Regis Pomes, Paul Chow:
A Scalable FPGA-based Multiprocessor.
111-120
Electronic Edition (link) BibTeX
- Charles L. Cathey, Jason D. Bakos, Duncan A. Buell:
A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism.
121-130
Electronic Edition (link) BibTeX
- Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown:
A Multithreaded Soft Processor for SoPC Area Reduction.
131-142
Electronic Edition (link) BibTeX
Session 6:
Graph Algorithms
- Michael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomas E. Uribe, Thomas F. Knight Jr., André DeHon:
GraphStep: A System Architecture for Sparse-Graph Algorithms.
143-151
Electronic Edition (link) BibTeX
- Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan:
Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths.
152-164
Electronic Edition (link) BibTeX
Session 7:
Power and Energy Optimization
- Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle:
A Field Programmable RFID Tag and Associated Design Flow.
165-174
Electronic Edition (link) BibTeX
- Robert G. Dimond, Oskar Mencer, Wayne Luk:
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA.
175-184
Electronic Edition (link) BibTeX
- Matthew French, Li Wang, Michael J. Wirthlin:
Power Visualization, Analysis, and Optimization Tools for FPGAs.
185-194
Electronic Edition (link) BibTeX
Session 8:
Network Technology
Session 9:
Biomedical and Cryptographic Applications
- Martin C. Herbordt, Josh Model, Yongfeng Gu, Bharat Sukhwani, Tom Van Court:
Single Pass, BLAST-Like, Approximate String Matching on FPGAs.
217-226
Electronic Edition (link) BibTeX
- Kevin Whitton, Xiaobo Sharon Hu, Cedric X. Yu, Danny Z. Chen:
An FPGA Solution for Radiation Dose Calculation.
227-236
Electronic Edition (link) BibTeX
- Andrey Bogdanov, M. C. Mertens:
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2).
237-248
Electronic Edition (link) BibTeX
Session 10:
Arithmetic
Posters
- Evgeny Fiksman, Yitzhak Birk, Oskar Mencer:
ASC-Based Acceleration in an FPGA with a Processor Core Using Software-Only Skills.
271-272
Electronic Edition (link) BibTeX
- Shannon Koh, Oliver Diessel:
COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs.
273-274
Electronic Edition (link) BibTeX
- Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design.
275-276
Electronic Edition (link) BibTeX
- Gang Wang, Wenrui Gong, Ryan Kastner:
Defect-Tolerant Nanocomputing Using Bloom Filters.
277-278
Electronic Edition (link) BibTeX
- Reid B. Porter, Jan R. Frigo, Maya Gokhale, Christophe Wolinski, François Charot, Charles Wagner:
A Programmable, Maximal Throughput Architecture for Neighborhood Image Processing.
279-280
Electronic Edition (link) BibTeX
- Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann, John A. Williams:
VPN Acceleration Using Reconfigurable System-On-Chip Technology.
281-282
Electronic Edition (link) BibTeX
- Chuan He, Guan Qin, Mi Lu, Wei Zhao:
An Optimized Finite Difference Computing Engine on FPGAs.
283-284
Electronic Edition (link) BibTeX
- Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi:
Highly Efficient String Matching Circuit for IDS with FPGA.
285-286
Electronic Edition (link) BibTeX
- Rafael A. Arce-Nazario, Manuel Jiménez, Domingo Rodríguez:
Effects of High-Level Discrete Signal Transform Formulations on Partitioning for Multi-FPGA Architectures.
287-288
Electronic Edition (link) BibTeX
- K. N. Vikram, V. Vasudevan:
Scheduling divisible loads on partially reconfigurable hardware.
289-290
Electronic Edition (link) BibTeX
- Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shibata, Keiichi Yasumoto, Minoru Ito:
General Architecture for Hardware Implementation of Genetic Algorithm.
291-292
Electronic Edition (link) BibTeX
- Yousef El-Kurdi, Warren J. Gross, Dennis Giannacopoulos:
Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs.
293-294
Electronic Edition (link) BibTeX
- Arpith C. Jacob, Brandon Harris, Jeremy Buhler, Roger D. Chamberlain, Young H. Cho:
Scalable Softcore Vector Processor for Biosequence Applications.
295-296
Electronic Edition (link) BibTeX
- Oliver Pell, Wayne Luk:
Generating Parametrised Hardware Libraries from Higher-Order Descriptions.
297-298
Electronic Edition (link) BibTeX
- Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones:
Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM).
299-300
Electronic Edition (link) BibTeX
- Gerhard Lienhart, Guillermo Marcus Martinez, Andreas Kugel, Reinhard Männer:
Rapid Design of Special-Purpose Pipeline Processors with FPGAs and its Application to Computational Fluid Dynamics.
301-302
Electronic Edition (link) BibTeX
- Michael R. Bodnar, John R. Humphrey, Petersen F. Curt, James P. Durbano, Dennis W. Prather:
Floating-Point Accumulation Circuit for Matrix Applications.
303-304
Electronic Edition (link) BibTeX
- Tom Van Court, Martin C. Herbordt:
Application-Specific Memory Interleaving Enables High Performance in FPGA-based Grid Computations.
305-306
Electronic Edition (link) BibTeX
- Kyprianos Papademetriou, Apostolos Dollas:
A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable Systems.
307-308
Electronic Edition (link) BibTeX
- Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones:
A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture.
309-310
Electronic Edition (link) BibTeX
- Sandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler:
COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking.
311-312
Electronic Edition (link) BibTeX
- Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann:
FPGAs, GPUs and the PS2 - A Single Programming Methodology.
313-314
Electronic Edition (link) BibTeX
- Yongfeng Gu, Tom Van Court, Martin C. Herbordt:
Integrating FPGA Acceleration into the Protomol Molecular Dynamics Code: Preliminary Report.
315-316
Electronic Edition (link) BibTeX
- Charlie Ross, A. P. Wim Böhm:
A Co-Verification Tool for a High Level Language Compiler for FPGAs.
317-318
Electronic Edition (link) BibTeX
- Dionissios Efstathiou, Konstantinos Kazakos, Apostolos Dollas:
Parrotfish: Task Distribution in a Low Cost Autonomous ad hoc Sensor Network through Dynamic Runtime Reconfiguration.
319-320
Electronic Edition (link) BibTeX
- John Maher, Brian McGinley, Patrick Rocke, Fearghal Morgan:
Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices.
321-322
Electronic Edition (link) BibTeX
- Heather Quinn, Debayan Bhaduri, Christof Teuscher, Paul Graham, Maya Gokhale:
The STAR-C Truth: Analyzing Reconfigurable Supercomputing Reliability.
323-324
Electronic Edition (link) BibTeX
- Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas:
Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs.
325-326
Electronic Edition (link) BibTeX
- Shobana Padmanabhan, Moshe Looks, Dan Legorreta, Young H. Cho, John W. Lockwood:
Hierarchical Clustering using Reconfigurable Devices.
327-328
Electronic Edition (link) BibTeX
- S. Dai, Elaheh Bozorgzadeh:
CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures.
329-330
Electronic Edition (link) BibTeX
- Allen Michalski, Duncan A. Buell:
A Scalable Architecture for RSA Cryptography on Large FPGAs.
331-332
Electronic Edition (link) BibTeX
- Kendall Ananyi, Daler N. Rakhmatov:
Design of a Reconfigurable Processor for NIST Prime Field ECC.
333-334
Electronic Edition (link) BibTeX
- Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arif Rahman:
Switch Box Architectures for Three-Dimensional FPGAs.
335-336
Electronic Edition (link) BibTeX
- James Moscola, Young H. Cho, John W. Lockwood:
A Scalable Hybrid Regular Expression Pattern Matcher.
337-338
Electronic Edition (link) BibTeX
- Cao Liang, Jing Ma, Xin-Ming Huang:
Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms.
339-340
Electronic Edition (link) BibTeX
- Jia Ming Mar, Alessandro Bissacco, Stefano Soatto, Soheil Ghiasi:
High Performance Feature Detection on a Reconfigurable Co-Processor.
341-342
Electronic Edition (link) BibTeX
- Michael J. Wirthlin, Welson Sun:
DSynth: A Pipeline Synthesis Environment for FPGAs.
343-344
Electronic Edition (link) BibTeX
- Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier:
Template-Based Generation of Streaming Accelators from a High Level Presentation.
345-346
Electronic Edition (link) BibTeX
- Brad Matthews, Itamar Elhanany:
Scalable Hardware Architecture for Real-Time Dynamic Programming Applications.
347-348
Electronic Edition (link) BibTeX
- K. Scott Hemmert, Keith D. Underwood:
Open Source High Performance Floating-Point Modules.
349-350
Electronic Edition (link) BibTeX
- John A. Williams, Irfan Syed, J. Wu, Neil W. Bergmann:
A Reconfigurable Cluster-on-Chip Architecture with MPI Communication Layer.
351-352
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:11:55 2009
by Michael Ley (ley@uni-trier.de)
