Qingfeng Zhuge

2008
39	EE	Qingfeng Zhuge, Chun Jason Xue, Meikang Qiu, Jingtong Hu, Edwin Hsing-Mean Sha: Timing optimization via nest-loop pipelining considering code size. Microprocessors and Microsystems - Embedded Hardware Design 32(7): 351-363 (2008)
2007
38	EE	Chun Xue, Zili Shao, Meilin Liu, Qingfeng Zhuge, Edwin Hsing-Mean Sha: Parallel Network Intrusion Detection on Reconfigurable Platforms. EUC 2007: 75-86
37	EE	Bin Xiao, Jiannong Cao, Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha: Analysis and algorithms design for the partition of large-scale adaptive mobile wireless networks. Computer Communications 30(8): 1899-1912 (2007)
2006
36	EE	Mei Kang Qiu, Chun Xue, Qingfeng Zhuge, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha: Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability. ASAP 2006: 178-181
35	EE	Mei Kang Qiu, Chun Xue, Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha: Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network. EUC 2006: 25-34
34	EE	Zili Shao, Bin Xiao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha: Loop scheduling with timing and switching-activity minimization for VLIW DSP. ACM Trans. Design Autom. Electr. Syst. 11(1): 165-185 (2006)
33	EE	Zili Shao, Chun Xue, Qingfeng Zhuge, Mei Kang Qiu, Bin Xiao, Edwin Hsing-Mean Sha: Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software. IEEE Trans. Computers 55(4): 443-453 (2006)
32	EE	Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, Meikang Qiu, Edwin Hsing-Mean Sha: Design optimization and space minimization considering timing and code size via retiming and unfolding. Microprocessors and Microsystems 30(4): 173-183 (2006)
2005
31	EE	Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha: High-level synthesis for DSP applications using heterogeneous functional units. ASP-DAC 2005: 302-304
30	EE	Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Mei Kang Qiu, Edwin Hsing-Mean Sha: Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs. EUC 2005: 121-130
29		Mei Kang Qiu, Meilin Liu, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Zili Shao: Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems. IASTED PDCS 2005: 295-300
28	EE	Ying Chen, Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha: Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems. ICPADS (2) 2005: 2-6
27	EE	Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Meikang Qiu, Edwin Hsing-Mean Sha: Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size. ISPAN 2005: 126-131
26	EE	Zili Shao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao: Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software. ITCC (1) 2005: 780-785
25	EE	Zili Shao, Qingfeng Zhuge, Chun Xue, Edwin Hsing-Mean Sha: Efficient Assignment and Scheduling for Heterogeneous DSP Systems. IEEE Trans. Parallel Distrib. Syst. 16(6): 516-525 (2005)
2004
24	EE	Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, Edwin Hsing-Mean Sha: Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications. ASAP 2004: 224-234
23	EE	Meilin Liu, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha: General loop fusion technique for nested loops considering timing and code size. CASES 2004: 190-201
22	EE	Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha, Bin Xiao: Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures. EUC 2004: 53-63
21	EE	Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha: Timing Optimization of Nested Loops Considering Code Size for DSP Applications. ICPP 2004: 475-482
20	EE	Zili Shao, Qingfeng Zhuge, Yi He, Chun Xue, Meilin Liu, Edwin Hsing-Mean Sha: Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units. IPDPS 2004
19		Meilin Liu, Qingfeng Zhuge, Zili Shao, Kevin F. Chen, Edwin Hsing-Mean Sha: Loop Fusion via Retiming for DSP Applications. ISCA PDCS 2004: 403-408
18	EE	Bin Xiao, Jiannong Cao, Qingfeng Zhuge, Yi He, Edwin Hsing-Mean Sha: Approximation Algorithms Design for Disk Partial Covering Problem. ISPAN 2004: 104-110
17	EE	Bin Xiao, Jiannong Cao, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha: Dynamic Update of Shortest Path Tree in OSPF. ISPAN 2004: 18-23
16	EE	Zili Shao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao: Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks. ITCC (1) 2004: 409-413
15		Bin Xiao, Qingfeng Zhuge, Edwin Hsing-Mean Sha: Efficient Algorithms for Dynamic Update of Shortest Path Tree in Networking. I. J. Comput. Appl. 11(1): 60-75 (2004)
14	EE	Zili Shao, Qingfeng Zhuge, Youtao Zhang, Edwin Hsing-Mean Sha: Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors. IJHPCN 1(1/2/3): 4-16 (2004)
2003
13	EE	Zili Shao, Qingfeng Zhuge, Yi He, Edwin Hsing-Mean Sha: Defending Embedded Systems Against Buffer Overflow via Hardware/Software. ACSAC 2003: 352-363
12	EE	Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-Mean Sha: Design space minimization with timing and code size optimization for embedded DSP. CODES+ISSS 2003: 144-149
11		Bin Xiao, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha: Design and Analysis of Improved Shortest Path Tree Update for Network Routing. ISCA PDCS 2003: 82-87
10	EE	Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai: Loop scheduling for minimizing schedule length and switching activities. ISCAS (5) 2003: 109-112
9	EE	Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai: An Integrated Framework of Design Optimization and Space Minimization for DSP applications. ISCAS (5) 2003: 601-604
8	EE	Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha: Code size reduction technique and implementation for software-pipelined DSP applications. ACM Trans. Embedded Comput. Syst. 2(4): 590-613 (2003)
2002
7		Bin Xiao, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai: Analysis and Algorithms for Partitioning of Large-scale Adaptive Mobile Networks. IASTED PDCS 2002: 302-308
6	EE	Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha: Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications. ICPP 2002: 613-620
5	EE	Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha: Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP. IPDPS 2002
4	EE	Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha: Performance optimization of multiple memory architectures for DSP. ISCAS (5) 2002: 469-472
3	EE	Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge: Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops. ISSS 2002: 144-149
2001
2		Bin Xiao, Qingfeng Zhuge, Edwin Hsing-Mean Sha: Efficient Update of Shortest Path Algorithms for Network Routing. ISCA PDCS 2001: 315-320
1		Zhong Wang, Qingfeng Zhuge, Edwin Hsing-Mean Sha: Scheduling and partitioning for multiple loop nests. ISSS 2001: 183-188

Coauthor Index

1	Jiannong Cao	[17] [18] [37]
2	Kevin F. Chen	[19]
3	Ying Chen	[28]
4	Yi He	[13] [18] [20]
5	Jingtong Hu	[39]
6	Meilin Liu	[19] [20] [22] [23] [24] [27] [29] [30] [32] [35] [36] [38]
7	Chantana Phongpensri (Chantana Chantrapornchai)	[3] [7] [9] [10]
8	Meikang Qiu (Mei Kang Qiu)	[27] [29] [30] [32] [33] [35] [36] [39]
9	Edwin Hsing-Mean Sha	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39]
10	Zili Shao	[3] [6] [10] [11] [12] [13] [14] [16] [17] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38]
11	Zhong Wang	[1]
12	Bin Xiao	[2] [3] [4] [5] [7] [8] [11] [12] [15] [16] [17] [18] [22] [24] [26] [28] [31] [33] [34] [37]
13	Chun Jason Xue (Chun Xue)	[16] [20] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [38] [39]
14	Youtao Zhang	[14]