2007 |
50 | EE | Luong Dinh Hung,
Hidetsugu Irie,
Masahiro Goshima,
Shuichi Sakai:
Utilization of SECDED for soft error and variation-induced defect tolerance in caches.
DATE 2007: 1134-1139 |
49 | EE | Tomoyoshi Kinoshita,
Ibuki Handa,
Makoto Muto,
Shuichi Sakai,
Hidehiko Tanaka:
Musical part separation based on perceptual hierarchy.
Systems and Computers in Japan 38(2): 91-100 (2007) |
2006 |
48 | EE | Satoshi Katsunuma,
Hiroyuki Kurita,
Ryota Shioya,
Kazuto Shimizu,
Hidetsugu Irie,
Masahiro Goshima,
Shuichi Sakai:
Base Address Recognition with Data Flow Tracking for Injection Attack Detection.
PRDC 2006: 165-172 |
47 | EE | Luong Dinh Hung,
Masahiro Goshima,
Shuichi Sakai:
SEVA: A Soft-Error- and Variation-Aware Cache Architecture.
PRDC 2006: 47-54 |
2005 |
46 | EE | Reiko Hamada,
Jun Okabe,
Ichiro Ide,
Shin'ichi Satoh,
Shuichi Sakai,
Hidehiko Tanaka:
Cooking navi: assistant for daily cooking in kitchen.
ACM Multimedia 2005: 371-374 |
45 | EE | Luong Dinh Hung,
Masahiro Goshima,
Shuichi Sakai:
Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag.
ICCD 2005: 342-350 |
44 | EE | Luong Dinh Hung,
Shuichi Sakai:
Dynamic Estimation of Task Level Parallelism with Operating System Support.
ISPAN 2005: 358-363 |
43 | EE | Koichi Miura,
Motomu Takano,
Reiko Hamada,
Ichiro Ide,
Shuichi Sakai,
Hidehiko Tanaka:
Associating semantically structured cooking videos with their preparation steps.
Systems and Computers in Japan 36(2): 51-62 (2005) |
2004 |
42 | EE | Reiko Hamada,
Koichi Miura,
Ichiro Ide,
Shin'ichi Satoh,
Shuichi Sakai,
Hidehiko Tanaka:
Multimedia Integration for Cooking Video Indexing.
PCM (2) 2004: 657-664 |
2003 |
41 | EE | Koichi Miura,
Reiko Hamada,
Ichiro Ide,
Shuichi Sakai,
Hidehiko Tanaka:
Associating Cooking Video Segments with Preparation Steps.
CIVR 2003: 174-183 |
40 | EE | Hideyuki Miura,
Luong Dinh Hung,
Chitaka Iwama,
Daisuke Tashiro,
Niko Demus Barli,
Shuichi Sakai,
Hidehiko Tanaka:
Compiler-Assisted Thread Level Control Speculation.
Euro-Par 2003: 603-608 |
39 | EE | Yoshimitsu Yanagawa,
Luong Dinh Hung,
Chitaka Iwama,
Niko Demus Barli,
Shuichi Sakai,
Hidehiko Tanaka:
Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors.
HiPC 2003: 393-404 |
38 | | Shuichi Sakai,
Mitsunori Togasaki,
Koichi Yamazaki:
A note on greedy algorithms for the maximum weighted independent set problem.
Discrete Applied Mathematics 126(2-3): 313-322 (2003) |
37 | EE | Ichiro Ide,
Reiko Hamada,
Shuichi Sakai,
Hidehiko Tanaka:
Compilation of dictionaries for semantic attribute analysis of television news captions.
Systems and Computers in Japan 34(12): 32-44 (2003) |
2002 |
36 | EE | Shuichi Sakai:
CMP on SoC: Architect's View.
ISSS 2002: 101-102 |
2001 |
35 | EE | Chitaka Iwama,
Niko Demus Barli,
Shuichi Sakai,
Hidehiko Tanaka:
Improving Conditional Branch Prediction on Speculative Multithreading Architectures.
Euro-Par 2001: 413-417 |
2000 |
34 | EE | Ichiro Ide,
Reiko Hamada,
Shuichi Sakai,
Hidehiko Tanaka:
Scene identification in news video by character region segmentation.
ACM Multimedia Workshops 2000: 195-200 |
33 | EE | Reiko Hamada,
Ichiro Ide,
Shuichi Sakai:
Associating cooking video with related textbook.
ACM Multimedia Workshops 2000: 237-241 |
32 | EE | Reiko Hamada,
Ichiro Ide,
Shuichi Sakai,
Hidehiko Tanaka:
Structural analysis of cooking preparation steps in Japanese.
IRAL 2000: 157-164 |
1999 |
31 | EE | Reiko Hamada,
Ichiro Ide,
Shuichi Sakai,
Hidehiko Tanaka:
Associating video with related documents.
ACM Multimedia (2) 1999: 17-20 |
30 | EE | Masaaki Honda,
Takeo Igarashi,
Hidehiko Tanaka,
Shuichi Sakai:
Integrated Manipulation: Context-Aware Manipulation of 2D Diagrams.
ACM Symposium on User Interface Software and Technology 1999: 159-160 |
29 | EE | Antonio Magnaghi,
Shuichi Sakai,
Hidehiko Tanaka:
Inter-procedural Analysis for Parallelization of Java Programs.
ACPC 1999: 594-595 |
28 | EE | Ichiro Ide,
Reiko Hamada,
Shuichi Sakai,
Hidehiko Tanaka:
Relating Graphical Features with Concept Classes for Automatic News Video Indexing.
Intelligent Information Integration 1999 |
1997 |
27 | EE | Yuetsu Kodama,
Hirofumi Sakane,
Hanpei Koike,
Mitsuhisa Sato,
Shuichi Sakai,
Yoshinori Yamaguchi:
Parallel Execution of Radix Sort Program Using Fine-Grain Communication.
IEEE PACT 1997: 136-145 |
26 | EE | Mitsuhisa Sato,
Yuetsu Kodama,
Hirofumi Sakane,
Hayato Yamana,
Shuichi Sakai,
Yoshinori Yamaguchi:
Experience with Fine-Grain Communication in EM-X Multiprocessor for Parallel Sparse Matrix Computation.
IPPS 1997: 242-248 |
25 | EE | Andrew Sohn,
Yuetsu Kodama,
Jui Ku,
Mitsuhisa Sato,
Hirofumi Sakane,
Hayato Yamana,
Shuichi Sakai,
Yoshinori Yamaguchi:
Fine-Grain Multithreading with the EM-X Multiprocessor.
SPAA 1997: 189-198 |
1995 |
24 | EE | Yuetsu Kodama,
Hirohumi Sakane,
Mitsuhisa Sato,
Hayato Yamana,
Shuichi Sakai,
Yoshinori Yamaguchi:
The EM-X Parallel Computer: Architecture and Basic Performance.
ISCA 1995: 14-23 |
23 | EE | Hayato Yamana,
Mitsuhisa Sato,
Yuetsu Kodama,
Hirofumi Sakane,
Shuichi Sakai,
Yoshinori Yamaguchi:
A Macrotask-level Unlimited Speculative Execution on Multiprocessors.
International Conference on Supercomputing 1995: 328-337 |
22 | | Atsushi Hori,
Takashi Yokota,
Yutaka Ishikawa,
Shuichi Sakai,
Hiroki Konaka,
Munenori Maeda,
Takashi Tomokiyo,
Jörg Nolte,
Hiroshi Matsuoka,
Kazuaki Okamoto,
Hideo Hirono:
Time Space Sharing Scheduling and Architectural Support.
JSSPP 1995: 92-105 |
21 | | Shuichi Sakai,
Yuetsu Kodama,
Mitsuhisa Sato,
Andrew Shaw,
Hiroshi Matsuoka,
Hideo Hirono,
Kazuaki Okamoto,
Takashi Yokota:
Reduced Interprocessor-Communication Architecture and its Implementation on EM-4.
Parallel Computing 21(5): 753-769 (1995) |
1994 |
20 | | Shuichi Sakai:
Overview of RWC Massively Parallel Computer Project.
HPDC 1994: 5 |
19 | | Mitsuhisa Sato,
Yuetsu Kodama,
Shuichi Sakai,
Yoshinori Yamaguchi:
EM-C: Programming with Explicit Parallelism and Locality for EM-4 Multiprocessor.
IFIP PACT 1994: 3-14 |
18 | | Mitsuhisa Sato,
Yuetsu Kodama,
Yoshinori Yamaguchi,
Shuichi Sakai:
Experience with Executing Shared Memory Programs using Fine-Grain Communication and Multithreading in EM-4.
IPPS 1994: 630-636 |
17 | EE | Andrew Sohn,
Mitsuhisa Sato,
Shuichi Sakai,
Yuetsu Kodama,
Yoshinori Yamaguchi:
Nonnumeric search results on the EM-4 distributed-memory multiprocessor.
SC 1994: 301-310 |
16 | | Mitsuhisa Sato,
Yuetsu Kodama,
Hirofumi Sakane,
Yoshinori Yamaguchi,
Shuichi Sakai:
Programming with Distributed Data Structure for EM-X Multiprocessor.
Theory and Practice of Parallel Programming 1994: 472-483 |
1993 |
15 | EE | Yuetsu Kodama,
Yasuhito Koumura,
Mitsuhisa Sato,
Hirohumi Sakane,
Shuichi Sakai,
Yoshinori Yamaguchi:
EMC-Y: Parallel Processing Element Optimizing Communication and Computation.
International Conference on Supercomputing 1993: 167-174 |
14 | EE | Shuichi Sakai,
Kazuaki Okamoto,
Hiroshi Matsuoka,
Hideo Hirono,
Yuetsu Kodama,
Mitsuhisa Sato:
Super-Threading: Architectural and Software Mechanisms for Optimizing Parallel Computation.
International Conference on Supercomputing 1993: 251-260 |
13 | | Shuichi Sakai,
Hiroshi Matsuoka,
Yuetsu Kodama,
Mitsuhisa Sato,
Andrew Shaw,
Hideo Hirono,
Kazuaki Okamoto,
Takashi Yokota:
RICA: Reduced Interprocessor-Communication Architecture - Concept and Mechanisms.
SPDP 1993: 122-127 |
12 | | Shuichi Sakai,
Yuetsu Kodama,
Yoshinori Yamaguchi:
Design and Implementation of a Circular Omega Network in the EM-4.
Parallel Computing 19(2): 125-142 (1993) |
1992 |
11 | | Yuetsu Kodama,
Shuichi Sakai,
Yoshinori Yamaguchi:
Evaluation of the EM-4 Highly Parallel Computer using a Game Tree Searching Problem.
FGCS 1992: 731-738 |
10 | EE | Kenji Toda,
Kenji Nishida,
Shuichi Sakai,
Toshio Shimada:
A priority forwarding scheme for real-time multistage interconnection networks.
IEEE Real-Time Systems Symposium 1992: 208-217 |
9 | | Mitsuhisa Sato,
Yuetsu Kodama,
Shuichi Sakai,
Yoshinori Yamaguchi,
Yasuhito Koumura:
Thread-based Programming for the EM-4 Hybrid Dataflow Machine.
ISCA 1992: 146-155 |
8 | | Kazuaki Okamoto,
Yuetsu Kodama,
Shuichi Sakai,
Yoshinori Yamaguchi:
Methodologies in development and testing of the dataflow machine EM-4.
Parallel Computing 18(8): 901-912 (1992) |
1991 |
7 | | Shuichi Sakai,
Yuetsu Kodama,
Yoshinori Yamaguchi:
Design and Implementation of a Versatile Interconnection Network in the EM-4.
ICPP (1) 1991: 426-430 |
6 | | Shuichi Sakai,
Yuetsu Kodama,
Yoshinori Yamaguchi:
Prototype Implementation of a Highly Parallel Dataflow Machine EM-4.
IPPS 1991: 278-286 |
5 | | Kenji Toda,
Kenji Nishida,
Yoshinobu Uchibori,
Shuichi Sakai,
Toshio Shimada:
Parallel Multi-Context Architecture with High-Speed Synchronization Mechanism.
IPPS 1991: 336-343 |
4 | EE | Yuetsu Kodama,
Shuichi Sakai,
Yoshinori Yamaguchi:
Load balancing by function distribution on the EM-4 prototype.
SC 1991: 522-531 |
1990 |
3 | EE | Toshitsugu Yuba,
Toshio Shimada,
Yoshinori Yamaguchi,
Kei Hiraki,
Shuichi Sakai:
Dataflow computer development in Japan.
ICS 1990: 140-147 |
1989 |
2 | | Yoshinori Yamaguchi,
Shuichi Sakai,
Kei Hiraki,
Yuetsu Kodama:
An Architectural Disgn of a Highly Parallel Dataflow Machine.
IFIP Congress 1989: 1155-1160 |
1 | EE | Shuichi Sakai,
Yoshinori Yamaguchi,
Kei Hiraki,
Yuetsu Kodama,
Toshitsugu Yuba:
An Architecture of a Dataflow Single Chip Processor.
ISCA 1989: 46-53 |