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Rajiv A. Ravindran

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2007
11EERajiv A. Ravindran, Michael L. Chu, Scott A. Mahlke: Compiler-managed partitioned data caches for low power. LCTES 2007: 237-247
10EEMichael L. Chu, Rajiv A. Ravindran, Scott A. Mahlke: Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures. MICRO 2007: 369-380
2005
9EERajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh S. Dasika, Eric D. Marsman, Robert M. Senger, Scott A. Mahlke, Richard B. Brown: Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache. CGO 2005: 179-190
8EERajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown: Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor. IEEE Trans. Computers 54(8): 998-1012 (2005)
2004
7EEManjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv A. Ravindran, Nathan Clark, Scott A. Mahlke: FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths. CGO 2004: 201-212
6EEMichael L. Chu, Kevin Fan, Rajiv A. Ravindran, Scott A. Mahlke: Cost-Sensitive Partitioning in an Architecture Synthesis System for Multicluster Processors. IEEE Micro 24(3): 10-20 (2004)
2003
5EEKevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke: Systematic Register Bypass Customization for Application-Specific Processors. ASAP 2003: 64-74
4EERajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown: Increasing the number of effective registers in a low-power processor using a windowed register file. CASES 2003: 125-136
2001
3EERajiv A. Ravindran, Rajat Moona: Retargetable Cache Simulation Using High Level Processor Models. ACSAC 2001: 114-129
2EERajiv A. Ravindran, Rajat Moona: Retargetable Program Profiling Using High Level Processor Models. HiPC 2001: 224-236
1EEScott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood: Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1355-1371 (2001)

Coauthor Index

1Richard B. Brown [4] [8] [9]
2Michael L. Chu [5] [6] [7] [10] [11]
3Nathan Clark [5] [7]
4Ganesh S. Dasika [4] [8] [9]
5Kevin Fan [5] [6] [7]
6Matthew R. Guthaus [4] [8]
7Manjunath Kudlur [7]
8Scott A. Mahlke [1] [4] [5] [6] [7] [8] [9] [10] [11]
9K. V. Manjunath [5]
10Eric D. Marsman [4] [8] [9]
11Rajat Moona [2] [3]
12Pracheeti D. Nagarkar [9]
13Michael S. Schlansker [1]
14Robert Schreiber [1]
15Robert M. Senger [4] [8] [9]
16Timothy Sherwood [1]
17Mikhail Smelyanskiy [5]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)