| 2005 |
|---|
| 8 | EE | Hans M. Jacobson,
Pradip Bose,
Zhigang Hu,
Alper Buyuktosunoglu,
Victor V. Zyuban,
Rick Eickemeyer,
Lee Eisen,
John Griswell,
Doug Logan,
Balaram Sinharoy,
Joel M. Tendler:
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.
HPCA 2005: 238-242 |
| 7 | EE | Joel M. Tendler:
Preface.
IBM Journal of Research and Development 49(4-5): 503- (2005) |
| 6 | EE | Balaram Sinharoy,
Ronald N. Kalla,
Joel M. Tendler,
Richard J. Eickemeyer,
Jody B. Joyner:
POWER5 system microarchitecture.
IBM Journal of Research and Development 49(4-5): 505-522 (2005) |
| 2004 |
|---|
| 5 | EE | Ronald N. Kalla,
Balaram Sinharoy,
Joel M. Tendler:
IBM Power5 Chip: A Dual-Core Multithreaded Processor.
IEEE Micro 24(2): 40-47 (2004) |
| 2002 |
|---|
| 4 | EE | Joel M. Tendler,
J. Steve Dodson,
J. S. Fields Jr.,
Hung Le,
Balaram Sinharoy:
POWER4 system microarchitecture.
IBM Journal of Research and Development 46(1): 5-26 (2002) |
| 3 | EE | Douglas C. Bossen,
Joel M. Tendler,
Kevin Reick:
Power4 System Design for High Reliability.
IEEE Micro 22(2): 16-24 (2002) |
| 1978 |
|---|
| 2 | EE | Joel M. Tendler,
Theodore A. Bickart,
Zdenek Picel:
A Stiffly Stable Integration Process Using Cyclic Composite Methods.
ACM Trans. Math. Softw. 4(4): 339-368 (1978) |
| 1 | EE | Joel M. Tendler,
Theodore A. Bickart,
Zdenek Picel:
Algorithm 534: STINT: STiff (differential equations) INTegrator [D2].
ACM Trans. Math. Softw. 4(4): 399-403 (1978) |
