| 2006 |
|---|
| 9 | EE | David J. Frank,
Ruchir Puri,
Dorel Toma:
Design and CAD challenges in 45nm CMOS and beyond.
ICCAD 2006: 329-333 |
| 8 | EE | David J. Frank,
Wilfried Haensch,
Ghavam Shahidi,
Omer H. Dokumaci:
Optimizing CMOS technology for maximum performance.
IBM Journal of Research and Development 50(4-5): 419-432 (2006) |
| 7 | EE | Kerry Bernstein,
David J. Frank,
Anne E. Gattiker,
Wilfried Haensch,
Brian L. Ji,
Sani R. Nassif,
Edward J. Nowak,
Dale J. Pearson,
Norman J. Rohrer:
High-performance CMOS variability in the 65-nm regime and beyond.
IBM Journal of Research and Development 50(4-5): 433-450 (2006) |
| 6 | EE | Anna W. Topol,
Douglas C. La Tulipe Jr.,
Leathen Shi,
David J. Frank,
Kerry Bernstein,
Steven E. Steen,
Arvind Kumar,
Gilbert U. Singco,
Albert M. Young,
Kathryn W. Guarini,
Mei-Kei Ieong:
Three-dimensional integrated circuits.
IBM Journal of Research and Development 50(4-5): 491-506 (2006) |
| 2002 |
|---|
| 5 | EE | David J. Frank:
Power-constrained CMOS scaling limits.
IBM Journal of Research and Development 46(2-3): 235-344 (2002) |
| 1997 |
|---|
| 4 | EE | David J. Frank,
Paul Solomon,
Scott Reynolds,
John Shin:
Supply and threshold voltage optimization for low power design.
ISLPED 1997: 317-322 |
| 1996 |
|---|
| 3 | EE | David J. Frank:
Comparison of high speed voltage-scaled conventional and adiabatic circuits.
ISLPED 1996: 377-380 |
| 1995 |
|---|
| 2 | EE | David J. Frank,
Paul M. Solomon:
Electroid-oriented adiabatic switching circuits.
ISLPD 1995: 197-202 |
| 1 | | Yuan Taur,
Yuh-Jier Mii,
David J. Frank,
H.-S. Philip Wong,
Douglas A. Buchanan,
Shalom J. Wind,
Stephen A. Rishton,
Watson A. Sai-Halasz,
Edward J. Nowak:
CMOS scaling into the 21st century: 0.1 µm and beyond.
IBM Journal of Research and Development 39(1-2): 245-260 (1995) |
