11. ASYNC 2005: New York, NY, USA

11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA. IEEE Computer Society 2005, ISBN 0-7695-2305-6 BibTeX

Invited Talk 1

Robert P. Colwell: Deep Pipelines vs. Risk and Power Walls. BibTeX

Circuit Techniques

Suwen Yang, Brian D. Winters, Mark R. Greenstreet:
Energy Efficient Surfing. 2-11
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Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Ivan E. Sutherland:
GasP Control for Domino Circuits. 12-22
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Tin Wai Kwan, Maitham Shams:
Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic. 23-32
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On-Chip Networks

Tobias Bjerregaard, Jens Sparsø:
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip. 34-43
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Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar:
An Asynchronous Router for Multiple Service Levels Networks on Chip. 44-53
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Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin:
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. 54-63
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Clocking and Synchronization

Joep L. W. Kessels:
Register Communication between Mutually Asynchronous Domains. 66-75
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Milos Krstic, Eckhard Grass, Christian Stahl:
Request-Driven GALS Technique for Wireless Communication System. 76-85
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Scott Fairbanks, Simon W. Moore:
Self-Timed Circuitry for Global Clocking. 86-96
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Invited Talk 2

Robert J. Drost, Ivan E. Sutherland: Proximity Communication and Time. BibTeX

Design Analysis

Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Stevens:
Modeling and Verifying Circuits Using Generalized Relative Timing. 98-108
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Vassilis Zebilis, Christos P. Sotiriou:
Controlling Event Spacing in Self-Timed Rings. 109-115
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Konrad J. Kulikowski, Ming Su, Alexander B. Smirnov, Alexander Taubin, Mark G. Karpovsky, Daniel MacDonald:
Delay Insensitive Encoding and Power Analysis: A Balancing Act. 116-125
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Design Implementations

Justin Hensley, Anselmo Lastra, Montek Singh:
A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier. 128-137
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Yee William Li, Kenneth L. Shepard, Yannis P. Tsividis:
Continuous-Time Digital Signal Processors. 138-143
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Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar:
BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor. 144-154
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Test and Reliability

Wonjin Jang, Alain J. Martin:
SEU-Tolerant QDI Circuits. 156-165
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Frank te Beest, Ad M. G. Peeters:
A Multiplexor Based Test Method for Self-Timed Circuits. 166-175
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Invited Tutorial

Phillip Restle, Kenneth L. Shepard: New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems. BibTeX

Encoding and Synthesis

Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers:
High Level Synthesis of Timed Asynchronous Circuits. 178-189
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Nikolai Starodoubtsev, Sergei Bystrov:
Behavior and Synthesis of Two-Input Gate Asynchronous Circuits. 190-200
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Frederic Worm, Patrick Thiran, Paolo Ienne:
A Unified Coding Framework for Delay-Insensitivity. 201-211
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