Nobuhiro Tomabechi

2005
8	EE	Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi: VLSI architecture based on packet data transfer scheme and its application. ISCAS (2) 2005: 1786-1789
2002
7	EE	Nobuhiro Tomabechi, Teruki Ito: Design of a high-speed RSA encryption processor based on the residue table for redundant binary numbers. Systems and Computers in Japan 33(5): 1-10 (2002)
2000
6	EE	Yoshichika Fujioka, Nobuhiro Tomabechi: Design of a WSI scale parallel processor for intelligent robot control based on a dynamic reconfiguration of multi-operand arithmetic units. Systems and Computers in Japan 31(12): 33-42 (2000)
1999
5	EE	Nobuhiro Tomabechi: Multi-Dimensional Subsystem-Dividing for Yield Enhancement in Defect-Tolerant WSI Systems. DFT 1999: 40-45
1998
4	EE	Shyouji Kanazawa, Nobuhiro Tomabechi: Redundancy design of a wafer scale two-dimensional FFT processor. Systems and Computers in Japan 29(10): 83-91 (1998)
1997
3	EE	Nobuhiro Tomabechi: CAI oriented algorithm for Boolean-function minimization based on the ternaryKarnaugh map. Systems and Computers in Japan 28(12): 1-10 (1997)
2	EE	Nobuhiro Tomabechi, Shyouji Kanazawa: Redundancy design of a wafer scale and high-speed FFT processor. Systems and Computers in Japan 28(6): 18-29 (1997)
1	EE	Nobuhiro Tomabechi: The effect of hardware needed for redundant interconnection lines and exchangingswitches on the yield of VLSI chips with redundan. Systems and Computers in Japan 28(8-9): 8-16 (1997)

Coauthor Index

1	Yoshichika Fujioka	[6] [8]
2	Yuya Homma	[8]
3	Teruki Ito	[7]
4	Michitaka Kameyama	[8]
5	Shyouji Kanazawa	[2] [4]

Colors in the list of coauthors