| 2001 |
|---|
| 11 | EE | Rita Yu Chen,
Mary Jane Irwin,
Raminder Singh Bajwa:
Architecture-level power estimation and design experiments.
ACM Trans. Design Autom. Electr. Syst. 6(1): 50-66 (2001) |
| 1998 |
|---|
| 10 | EE | Rita Yu Chen,
Robert Michael Owens,
Mary Jane Irwin,
Raminder Singh Bajwa:
Validation of an Architectural Level Power Analysis Technique.
DAC 1998: 242-245 |
| 9 | EE | Vladimir Stojanovic,
Vojin G. Oklobdzija,
Raminder Singh Bajwa:
A unified approach in the analysis of latches and flip-flops for low-power systems.
ISLPED 1998: 227-232 |
| 1997 |
|---|
| 8 | EE | Raminder Singh Bajwa,
Mitsuru Hiraki,
Hirotsugu Kojima,
Douglas J. Gorny,
Ken-ichi Nitta,
Avadhani Shridhar,
Koichi Seki,
Katsuro Sasaki:
Instruction buffering to reduce power in processors for signal processing.
IEEE Trans. VLSI Syst. 5(4): 417-424 (1997) |
| 1996 |
|---|
| 7 | EE | Mitsuru Hiraki,
Raminder Singh Bajwa,
Hirotsugu Kojima,
Douglas J. Gorny,
Ken-ichi Nitta,
Avadhani Shridhar,
Katsuro Sasaki,
Koichi Seki:
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer.
ISLPED 1996: 353-358 |
| 1995 |
|---|
| 6 | EE | Raminder Singh Bajwa,
Robert Michael Owens,
Mary Jane Irwin:
The MGAP's programming environment and the *C++ language.
ASAP 1995: 121-124 |
| 5 | EE | Robert Michael Owens,
Raminder Singh Bajwa,
Mary Jane Irwin:
Reducing the number of counters needed for integer multiplication.
IEEE Symposium on Computer Arithmetic 1995: 38-41 |
| 1994 |
|---|
| 4 | | Raminder Singh Bajwa,
Robert Michael Owens,
Mary Jane Irwin:
Area Time Trade-Offs in Micro-Grain VLSI Array Architectures.
IEEE Trans. Computers 43(10): 1121-1128 (1994) |
| 1993 |
|---|
| 3 | | Raminder Singh Bajwa,
Robert Michael Owens,
Mary Jane Irwin:
Image Processing with the MGAP: A Cost Effective Solution.
IPPS 1993: 439-443 |
| 2 | | Raminder Singh Bajwa,
Robert Michael Owens,
Mary Jane Irwin:
A Massively Parallel, Micro-Grained VLSI Architecture.
VLSI Design 1993: 250-255 |
| 1 | EE | Robert Michael Owens,
Thomas P. Kelliher,
Mary Jane Irwin,
Mohan Vishwanath,
Raminder Singh Bajwa,
W.-L. Yang:
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system.
IEEE Trans. VLSI Syst. 1(4): 491-502 (1993) |
