Douglas J. Gorny

1997
2	EE	Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki: Instruction buffering to reduce power in processors for signal processing. IEEE Trans. VLSI Syst. 5(4): 417-424 (1997)
1996
1	EE	Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki: Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. ISLPED 1996: 353-358

Coauthor Index

1	Raminder Singh Bajwa	[1] [2]
2	Mitsuru Hiraki	[1] [2]
3	Hirotsugu Kojima	[1] [2]
4	Ken-ichi Nitta	[1] [2]
5	Katsuro Sasaki	[1] [2]
6	Koichi Seki	[1] [2]
7	Avadhani Shridhar	[1] [2]