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Douglas J. Gorny

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1997
2EERaminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki: Instruction buffering to reduce power in processors for signal processing. IEEE Trans. VLSI Syst. 5(4): 417-424 (1997)
1996
1EEMitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki: Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. ISLPED 1996: 353-358

Coauthor Index

1Raminder Singh Bajwa [1] [2]
2Mitsuru Hiraki [1] [2]
3Hirotsugu Kojima [1] [2]
4Ken-ichi Nitta [1] [2]
5Katsuro Sasaki [1] [2]
6Koichi Seki [1] [2]
7Avadhani Shridhar [1] [2]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)