| 2005 |
|---|
| 3 | EE | Toshikazu Suzuki,
Yoshinobu Yamagami,
Ichiro Hatanaka,
Akinori Shibayama,
Hironori Akamatsu,
Hiroyuki Yamauchi:
0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier.
IEICE Transactions 88-C(4): 630-638 (2005) |
| 1997 |
|---|
| 2 | EE | Hiroyuki Yamauchi,
Toru Iwata,
Hironori Akamatsu,
Akira Matsuzawa:
A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture.
IEEE Trans. VLSI Syst. 5(4): 377-387 (1997) |
| 1996 |
|---|
| 1 | EE | Hiroyuki Yamauchi,
Toru Iwata,
Hironori Akamatsu,
Akira Matsuzawa:
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes.
ISLPED 1996: 49-54 |
