2002 |
35 | EE | Alain Darte,
Robert Schreiber,
B. Ramakrishna Rau,
Frédéric Vivien:
Constructing and exploiting linear schedules with prescribed parallelism.
ACM Trans. Design Autom. Electr. Syst. 7(1): 159-172 (2002) |
34 | EE | Vinod Kathail,
Shail Aditya,
Robert Schreiber,
B. Ramakrishna Rau,
Darren C. Cronquist,
Mukund Sivaraman:
PICO: Automatically Designing Custom Computers.
IEEE Computer 35(9): 39-47 (2002) |
33 | EE | Robert Schreiber,
Shail Aditya,
Scott A. Mahlke,
Vinod Kathail,
B. Ramakrishna Rau,
Darren C. Cronquist,
Mukund Sivaraman:
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators.
VLSI Signal Processing 31(2): 127-142 (2002) |
2001 |
32 | EE | B. Ramakrishna Rau,
Michael S. Schlansker:
Embedded Computer Architecture and Automation.
IEEE Computer 34(4): 75-83 (2001) |
2000 |
31 | EE | Robert Schreiber,
Shail Aditya,
B. Ramakrishna Rau,
Vinod Kathail,
Scott A. Mahlke,
Santosh G. Abraham,
Greg Snider:
High-Level Synthesis of Nonprogrammable Hardware Accelerators.
ASAP 2000: 113- |
30 | EE | B. Ramakrishna Rau:
The era of embedded computing.
CASES 2000: 119 |
29 | EE | Santosh G. Abraham,
B. Ramakrishna Rau:
Efficient design space exploration in PICO.
CASES 2000: 71-79 |
28 | EE | B. Ramakrishna Rau,
Michael S. Schlansker:
Embedded Computing: New Directions in Architecture and Automation.
HiPC 2000: 225-244 |
27 | EE | Alain Darte,
Robert Schreiber,
B. Ramakrishna Rau,
Frédéric Vivien:
A Constructive Solution to the Juggling Problem in Processor Array Synthesis.
IPDPS 2000: 815-822 |
26 | EE | Shail Aditya,
Scott A. Mahlke,
B. Ramakrishna Rau:
Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats.
ACM Trans. Design Autom. Electr. Syst. 5(4): 752-773 (2000) |
25 | EE | Michael S. Schlansker,
B. Ramakrishna Rau:
EPIC: Explicititly Parallel Instruction Computing.
IEEE Computer 33(2): 37-45 (2000) |
1999 |
24 | EE | Shail Aditya,
B. Ramakrishna Rau,
Vinod Kathail:
Automatic Architectural Synthesis of VLIW and EPIC Processors.
ISSS 1999: 107-113 |
1998 |
23 | | John C. Gyllenhaal,
Wen-mei W. Hwu,
B. Ramakrishna Rau:
Optimization of Machine Descriptions for Efficient Use.
International Journal of Parallel Programming 26(4): 417-447 (1998) |
1996 |
22 | EE | John C. Gyllenhaal,
Wen-mei W. Hwu,
B. Ramakrishna Rau:
Optimization of Machine Descriptions for Efficient Use.
MICRO 1996: 349-358 |
21 | EE | Chandra Chekuri,
Richard Johnson,
Rajeev Motwani,
B. Natarajan,
B. Ramakrishna Rau,
Michael S. Schlansker:
Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks.
MICRO 1996: 58-67 |
1995 |
20 | EE | Richard E. Hank,
Wen-mei W. Hwu,
B. Ramakrishna Rau:
Region-based compilation: an introduction and motivation.
MICRO 1995: 158-168 |
1994 |
19 | EE | B. Ramakrishna Rau:
Iterative modulo scheduling: an algorithm for software pipelining loops.
MICRO 1994: 63-74 |
1993 |
18 | EE | Santosh G. Abraham,
Rabin A. Sugumar,
Daniel Windheiser,
B. Ramakrishna Rau,
Rajiv Gupta:
Predictability of load/store instruction latencies.
MICRO 1993: 139-152 |
17 | EE | B. Ramakrishna Rau:
Dynamically scheduled VLIW processors.
MICRO 1993: 80-92 |
16 | | Nancy J. Warter,
Scott A. Mahlke,
Wen-mei W. Hwu,
B. Ramakrishna Rau:
Reverse If-Conversion.
PLDI 1993: 290-299 |
15 | EE | Scott A. Mahlke,
William Y. Chen,
Roger A. Bringmann,
Richard E. Hank,
Wen-mei W. Hwu,
B. Ramakrishna Rau,
Michael S. Schlansker:
Sentinel Scheduling for VLIW and Superscalar Processors.
ACM Trans. Comput. Syst. 11(4): 376-408 (1993) |
1992 |
14 | | Scott A. Mahlke,
William Y. Chen,
Wen-mei W. Hwu,
B. Ramakrishna Rau,
Michael S. Schlansker:
Sentinel Scheduling for VLIW and Superscalar Processors.
ASPLOS 1992: 238-247 |
13 | EE | B. Ramakrishna Rau,
Michael S. Schlansker,
Parthasarathy P. Tirumalai:
Code generation schema for modulo scheduled loops.
MICRO 1992: 158-169 |
12 | | B. Ramakrishna Rau,
M. Lee,
Parthasarathy P. Tirumalai,
Michael S. Schlansker:
Register Allocation for Software Pipelined Loops.
PLDI 1992: 283-299 |
1991 |
11 | EE | B. Ramakrishna Rau:
Pseudo-Randomly Interleaved Memory.
ISCA 1991: 74-83 |
10 | | B. Ramakrishna Rau:
Data Flow and Dependence Analysis for Instruction Level Parallelism.
LCPC 1991: 236-250 |
1989 |
9 | | B. Ramakrishna Rau,
Michael S. Schlansker,
David W. L. Yen:
The Cydram 5 Stride-Insensitive Memory System.
ICPP (1) 1989: 242-246 |
8 | | B. Ramakrishna Rau,
David W. L. Yen,
Wei C. Yen,
Ross A. Towle:
The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs.
IEEE Computer 22(1): 12-35 (1989) |
1988 |
7 | | B. Ramakrishna Rau:
Cydra 5 Directed Dataflow Architecture.
COMPCON 1988: 106-113 |
1982 |
6 | EE | Pradip Bose,
B. Ramakrishna Rau,
Michael S. Schlansker:
Systematically derived instruction sets for high-level language support.
ACM Southeast Regional Conference 1982: 73-84 |
5 | | B. Ramakrishna Rau,
Christopher D. Glaeser,
E. M. Greenawalt:
Architectural Support for the Efficient Generation of Code for Horizontal Architectures.
ASPLOS 1982: 96-99 |
4 | EE | B. Ramakrishna Rau,
Christopher D. Glaeser,
Raymond L. Picard:
Efficient code generation for horizontal architectures: Compiler techniques and architectural support.
ISCA 1982: 131-139 |
1979 |
3 | | B. Ramakrishna Rau:
Program Behavior and the Performance of Interleaved Memories.
IEEE Trans. Computers 28(3): 191-199 (1979) |
2 | | B. Ramakrishna Rau:
Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System.
IEEE Trans. Computers 28(9): 678-681 (1979) |
1977 |
1 | | B. Ramakrishna Rau,
George E. Rossman:
The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units.
ISCA 1977: 80-89 |