| 2007 |
|---|
| 6 | EE | Dipanjan Gope,
Albert E. Ruehli,
Vikram Jandhyala:
Speeding Up PEEC Partial Inductance Computations Using a QR-Based Algorithm.
IEEE Trans. VLSI Syst. 15(1): 60-68 (2007) |
| 2006 |
|---|
| 5 | EE | Chuanyi Yang,
Swagato Chakraborty,
Dipanjan Gope,
Vikram Jandhyala:
A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structures.
DAC 2006: 1053-1056 |
| 2005 |
|---|
| 4 | EE | Dipanjan Gope,
Indranil Chowdhury,
Vikram Jandhyala:
DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures.
DAC 2005: 159-162 |
| 2004 |
|---|
| 3 | EE | Dipanjan Gope,
Swagato Chakraborty,
Vikram Jandhyala:
A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS.
DAC 2004: 794-799 |
| 2 | EE | Dipanjan Gope,
Vikram Jandhyala:
Oct-tree-based multilevel low-rank decomposition algorithm for rapid 3-D parasitic extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1575-1580 (2004) |
| 2002 |
|---|
| 1 | EE | Vikram Jandhyala,
Yong Wang,
Dipanjan Gope,
C.-J. Richard Shi:
Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes.
ISQED 2002: 38-42 |
