| |
| 2001 | ||
|---|---|---|
| 1 | EE | Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy: Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. ISLPED 2001: 267-270 |
| 1 | Aiqun Cao | [1] |
| 2 | Cheng-Kok Koh | [1] |
| 3 | Kaushik Roy | [1] |
| 4 | Naran Sirisantana | [1] |