| 2008 |
|---|
| 11 | EE | Wei Hu,
Yongxin Zhu,
Zonghua Gu,
Lei Jiang:
Pre-synthesis resource generation and estimation for transport-triggered architecture (TTA)-like architecture.
Microprocessors and Microsystems - Embedded Hardware Design 32(4): 234-242 (2008) |
| 2007 |
|---|
| 10 | EE | Rongrong Zhong,
Yongxin Zhu,
Weiwei Chen,
Mingliang Lin,
Weng-Fai Wong:
An Inter-Core Communication Enabled Multi-Core Simulator Based on SimpleScalar.
AINA Workshops (1) 2007: 758-763 |
| 9 | EE | Junjie Ni,
Yongxin Zhu,
Wei Guo:
An Improved RAIM Scheme for Processing Multiple Outliers in GNSS.
AINA Workshops (1) 2007: 840-845 |
| 2006 |
|---|
| 8 | EE | Yongxin Zhu,
Weng-Fai Wong,
Stefan Andrei:
Co-optimization of Performance and Power in a Superscalar Processor Design.
EUC Workshops 2006: 868-878 |
| 7 | EE | Xianhui He,
Yongxin Zhu,
Zhenxin Sun,
Yuzhuo Fu:
UML Based Evaluation of Reconfigurable Shape Adaptive DCT for Embedded Stream Processing.
EUC Workshops 2006: 898-907 |
| 2005 |
|---|
| 6 | EE | Zhenxin Sun,
Weng-Fai Wong,
Yongxin Zhu,
Santhosh Kumar Pilakkat:
Design of clocked circuits using UML.
ASP-DAC 2005: 901-904 |
| 5 | EE | Yongxin Zhu,
Weng-Fai Wong,
Stefan Andrei:
An integrated performance and power model for superscalar processor designs.
ASP-DAC 2005: 948-951 |
| 4 | EE | Yongxin Zhu,
Weng-Fai Wong,
Cheng-Kok Koh:
A Performance and Power Co-optimization Approach for Modern Processors.
CIT 2005: 822-828 |
| 3 | EE | Yongxin Zhu,
Zhenxin Sun,
Alexander Maxiaguine,
Weng-Fai Wong:
Using UML 2.0 for System Level Design of Real Time SoC Platforms for Stream Processing.
RTCSA 2005: 154-159 |
| 2 | EE | Stefan Andrei,
Wei-Ngan Chin,
Albert Mo Kim Cheng,
Yongxin Zhu:
Runtime-Coordinated Scalable Incremental Checksum Testing of Combinational Circuits.
RTCSA 2005: 357-360 |
| 2004 |
|---|
| 1 | EE | Alexander Maxiaguine,
Yongxin Zhu,
Samarjit Chakraborty,
Weng-Fai Wong:
Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs.
CODES+ISSS 2004: 128-133 |
