2005 |
8 | EE | Aiqun Cao,
Naran Sirisantana,
Cheng-Kok Koh,
Kaushik Roy:
Synthesis of skewed logic circuits.
ACM Trans. Design Autom. Electr. Syst. 10(2): 205-228 (2005) |
2004 |
7 | EE | Naran Sirisantana,
Kaushik Roy:
Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses.
IEEE Design & Test of Computers 21(1): 56-63 (2004) |
6 | EE | Naran Sirisantana,
Bipul Chandra Paul,
Kaushik Roy:
Enhancing Yield at the End of the Technology Roadmap.
IEEE Design & Test of Computers 21(6): 563-571 (2004) |
2003 |
5 | EE | Naran Sirisantana,
Kaushik Roy:
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies.
DATE 2003: 11160-11161 |
2002 |
4 | EE | Aiqun Cao,
Naran Sirisantana,
Cheng-Kok Koh,
Kaushik Roy:
Synthesis of Selectively Clocked Skewed Logic Circuits.
ISQED 2002: 229-234 |
3 | EE | Alexandre Solomatnikov,
Dinesh Somasekhar,
Naran Sirisantana,
Kaushik Roy:
Skewed CMOS: noise-tolerant high-performance low-power static circuit family.
IEEE Trans. VLSI Syst. 10(4): 469-476 (2002) |
2001 |
2 | EE | Naran Sirisantana,
Aiqun Cao,
Shawn Davidson,
Cheng-Kok Koh,
Kaushik Roy:
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications.
ISLPED 2001: 267-270 |
2000 |
1 | EE | Naran Sirisantana,
Liqiong Wei,
Kaushik Roy:
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness.
ICCD 2000: 227- |