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Naran Sirisantana

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2005
8EEAiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy: Synthesis of skewed logic circuits. ACM Trans. Design Autom. Electr. Syst. 10(2): 205-228 (2005)
2004
7EENaran Sirisantana, Kaushik Roy: Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses. IEEE Design & Test of Computers 21(1): 56-63 (2004)
6EENaran Sirisantana, Bipul Chandra Paul, Kaushik Roy: Enhancing Yield at the End of the Technology Roadmap. IEEE Design & Test of Computers 21(6): 563-571 (2004)
2003
5EENaran Sirisantana, Kaushik Roy: Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies. DATE 2003: 11160-11161
2002
4EEAiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy: Synthesis of Selectively Clocked Skewed Logic Circuits. ISQED 2002: 229-234
3EEAlexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy: Skewed CMOS: noise-tolerant high-performance low-power static circuit family. IEEE Trans. VLSI Syst. 10(4): 469-476 (2002)
2001
2EENaran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy: Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. ISLPED 2001: 267-270
2000
1EENaran Sirisantana, Liqiong Wei, Kaushik Roy: High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. ICCD 2000: 227-

Coauthor Index

1Aiqun Cao [2] [4] [8]
2Shawn Davidson [2]
3Cheng-Kok Koh [2] [4] [8]
4Bipul Chandra Paul (Bipul C. Paul) [6]
5Kaushik Roy [1] [2] [3] [4] [5] [6] [7] [8]
6Alexandre Solomatnikov [3]
7Dinesh Somasekhar [3]
8Liqiong Wei [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)