| |
| 2004 | ||
|---|---|---|
| 3 | EE | Sudheendra Hangal, Durgam Vahia, Chaiyasit Manovit, Juin-Yeu Joseph Lu, Sridhar Narayanan: TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model. ISCA 2004: 114-123 |
| 1998 | ||
| 2 | EE | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu: Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. DAC 1998: 632-637 |
| 1996 | ||
| 1 | EE | Juin-Yeu Joseph Lu, Jang Dae Kim, Shiu-Kai Chin: Hardware Composition with Hardware Flowcharts and Process Algebras. ICECCS 1996: 352- |
| 1 | Kuang-Chien Chen | [2] |
| 2 | Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng) | [2] |
| 3 | Shiu-Kai Chin | [1] |
| 4 | Sudheendra Hangal | [3] |
| 5 | Shi-Yu Huang | [2] |
| 6 | Jang Dae Kim | [1] |
| 7 | Chaiyasit Manovit | [3] |
| 8 | Sridhar Narayanan | [3] |
| 9 | Durgam Vahia | [3] |