Vivian Brégier

2005
1	EE	Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin: Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. VLSI-SoC 2005: 55-69

Coauthor Index

1	Laurent Fesquet	[1]
2	Bertrand Folco	[1]
3	Marc Renaudin	[1]